| Patent application number | Description | Published |
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| 20120112207 | METHOD TO REDUCE GROUND-PLANE POISONING OF EXTREMELY-THIN SOI (ETSOI) LAYER WITH THIN BURIED OXIDE - The present disclosure, which is directed to ultra-thin-body-and-BOX and Double BOX fully depleted SOI devices having an epitaxial diffusion-retarding semiconductor layer that slows dopant diffusion into the SOI channel, and a method of making these devices. Dopant concentrations in the SOI channels of the devices of the present disclosure having an epitaxial diffusion-retarding semiconductor layer between the substrate and SOI channel are approximately 50 times less than the dopant concentrations measured in SOI channels of devices without the epitaxial diffusion-retarding semiconductor layer. | 05-10-2012 |
| 20120211079 | SILICON PHOTOVOLTAIC ELEMENT AND FABRICATION METHOD - A method of forming a photovoltaic device that includes providing an absorption layer of a first crystalline semiconductor material having a first conductivity type, and epitaxially growing a second crystalline semiconductor layer of a second conductivity type that is opposite the first conductivity type. The first conductivity type may be p-type and the second conductivity type may be n-type, or the first conductivity type may be n-type and the second conductivity type may be p-type. The temperature of the epitaxially growing the second crystalline semiconductor layer does not exceed 500° C. Contacts are formed in electrical communication with the absorption layer and the second crystalline semiconductor layer. | 08-23-2012 |
| 20120255600 | METHOD OF BONDING AND FORMATION OF BACK SURFACE FIELD (BSF) FOR MULTI-JUNCTION III-V SOLAR CELLS - A photovoltaic device including at least one top cell that include at least one semiconductor material; a bottom cell of a germanium containing material having a thickness of 10 microns or less; and a back surface field (BSF) region provided by a eutectic alloy layer of aluminum and germanium on the back surface of the bottom cell of that is opposite the interface between the bottom cell and at least one of the top cells. The eutectic alloy of aluminum and germanium bonds the bottom cell of the germanium-containing material to a supporting substrate. | 10-11-2012 |
| 20120312362 | SILICON-CONTAINING HETEROJUNCTION PHOTOVOLTAIC ELEMENT AND DEVICE - A photovoltaic device is provided in which the tunneling barrier for hole collection at either the front contact or the back contact of a silicon heterojunction cell is reduced, without compromising the surface passivation either the front contact or at the back contact. This is achieved in the present disclosure by replacing the intrinsic and/or doped hydrogenated amorphous silicon (a-Si:H) layer(s) at the back contact or at the front contact with an intrinsic and/or doped layer(s) of a semiconductor material having a lower valence band-offset than that of a:Si—H with c-Si, and/or a higher activated doping concentration compared to that of doped hydrogenated amorphous Si. The higher level of activated doping is due to the higher doping efficiency of the back contact or front contact semiconductor material compared to that of amorphous Si, and/or modulation doping of the back or front contact semiconducting material. As a result, the tunneling barrier for hole collection is reduced and the cell efficiency is improved accordingly. | 12-13-2012 |
| 20120329197 | METHOD OF BONDING AND FORMATION OF BACK SURFACE FIELD (BSF) FOR MULTI-JUNCTION III-V SOLAR CELLS - A photovoltaic device including at least one top cell that include at least one III-V semiconductor material; a bottom cell of a germanium containing material having a thickness of | 12-27-2012 |
| 20120329206 | SILICON-CONTAINING HETEROJUNCTION PHOTOVOLTAIC ELEMENT AND DEVICE - In one embodiment, a method of forming a photovoltaic device is provided which includes providing an absorption layer comprising a silicon-containing semiconductor layer of a first conductivity type and having a top surface and a bottom surface that opposes the top surface. A front contact is formed on the top surface of the absorption layer, and a back contact is formed on the bottom surface of the absorption layer. The forming of the front contact and the back contact can occur in any order. The back contact that is formed comprises at least one back contact semiconductor material layer of the first conductivity type and having a lower band-offset than that of hydrogenated amorphous silicon with crystalline Si and/or a higher activated doping of the first conductivity type than that of the doped hydrogenated amorphous silicon layer. | 12-27-2012 |
| 20130019944 | METHOD OF STABILIZING HYDROGENATED AMORPHOUS SILICON AND AMORPHOUS HYDROGENATED SILICON ALLOYS - A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material. | 01-24-2013 |
| 20130019945 | METHOD OF STABILIZING HYDROGENATED AMORPHOUS SILICON AND AMORPHOUS HYDROGENATED SILICON ALLOYS - A method of forming a semiconductor material of a photovoltaic device that includes providing a surface of a hydrogenated amorphous silicon containing material, and annealing the hydrogenated amorphous silicon containing material in a deuterium containing atmosphere. Deuterium from the deuterium-containing atmosphere is introduced to the lattice of the hydrogenated amorphous silicon containing material through the surface of the hydrogenated amorphous silicon containing material. In some embodiments, the deuterium that is introduced to the lattice of the hydrogenated amorphous silicon containing material increases the stability of the hydrogenated amorphous silicon containing material. | 01-24-2013 |
| 20130025654 | MULTI-JUNCTION PHOTOVOLTAIC DEVICE AND FABRICATION METHOD - A method of forming a photovoltaic device that includes bonding a substrate to a germanium-containing semiconductor layer with a stressor layer, wherein the stressor layer cleaves the germanium-containing semiconductor layer. At least one semiconductor layer is formed on a cleaved surface of the germanium-containing semiconductor layer that is opposite the conductivity type of the germanium-containing semiconductor layer to provide a first solar cell. The first solar cell absorbs a first range of wavelengths. At least one second solar cell may be formed on the first solar cell, wherein the at least one second solar cell is composed of at least one semiconductor material to absorb a second range of wavelengths that is different than the first range wavelengths absorbed by the first solar cell. | 01-31-2013 |
| 20130025659 | MULTI-JUNCTION PHOTOVOLTAIC DEVICE AND FABRICATION METHOD - A method of forming a photovoltaic device that includes bonding a substrate to a germanium-containing semiconductor layer with a stressor layer, wherein the stressor layer cleaves the germanium-containing semiconductor layer. At least one semiconductor layer is formed on a cleaved surface of the germanium-containing semiconductor layer that is opposite the conductivity type of the germanium-containing semiconductor layer to provide a first solar cell. The first solar cell absorbs a first range of wavelengths. At least one second solar cell may be formed on the first solar cell, wherein the at least one second solar cell is composed of at least one semiconductor material to absorb a second range of wavelengths that is different than the first range wavelengths absorbed by the first solar cell. | 01-31-2013 |
| 20130092218 | BACK-SURFACE FIELD STRUCTURES FOR MULTI-JUNCTION III-V PHOTOVOLTAIC DEVICES - A multi-junction III-V photovoltaic device is provided that includes at least one top cell comprised of at least one III-V compound semiconductor material; and a bottom cell in contact with a surface of the at least one top cell. The bottom cell includes a germanium-containing layer in contact with the at least one top cell, at least one intrinsic hydrogenated silicon-containing layer in contact with a surface of the germanium-containing layer, and at least one doped hydrogenated silicon-containing layer in contact with a surface of the at least one intrinsic hydrogenated silicon-containing layer. The intrinsic and doped silicon-containing layers can be amorphous, nano/micro-crystalline, poly-crystalline or single-crystalline. | 04-18-2013 |
| 20130095598 | BACK-SURFACE FIELD STRUCTURES FOR MULTI-JUNCTION III-V PHOTOVOLTAIC DEVICES - A multi-junction III-V photovoltaic device is provided that includes at least one top cell comprised of at least one III-V compound semiconductor material; and a bottom cell in contact with a surface of the at least one top cell. The bottom cell includes a germanium-containing layer in contact with the at least one top cell, at least one intrinsic hydrogenated silicon-containing layer in contact with a surface of the germanium-containing layer, and at least one doped hydrogenated silicon-containing layer in contact with a surface of the at least one intrinsic hydrogenated silicon-containing layer. The intrinsic and doped silicon-containing layers can be amorphous, nano/micro-crystalline, poly-crystalline or single-crystalline. | 04-18-2013 |
| 20130244372 | SILICON PHOTOVOLTAIC ELEMENT AND FABRICATION METHOD - A method of forming a photovoltaic device that includes providing an absorption layer of a first crystalline semiconductor material having a first conductivity type, and epitaxially growing a second crystalline semiconductor layer of a second conductivity type that is opposite the first conductivity type. The first conductivity type may be p-type and the second conductivity type may be n-type, or the first conductivity type may be n-type and the second conductivity type may be p-type. The temperature of the epitaxially growing the second crystalline semiconductor layer does not exceed 500° C. Contacts are formed in electrical communication with the absorption layer and the second crystalline semiconductor layer. | 09-19-2013 |
| 20130307075 | CRYSTALLINE THIN-FILM TRANSISTORS AND METHODS OF FORMING SAME - Thin film transistors containing a gate structure on a crystalline semiconductor material including a crystalline active channel layer are provided. The gate structure of the present disclosure includes an insulator stack of, from bottom to top, a hydrogenated non-crystalline semiconductor material layer portion and a hydrogenated non-crystalline silicon nitride portion. Doped crystalline semiconductor source/drain regions are located on opposing sides of the gate structure and on surface portions of the crystalline semiconductor material. | 11-21-2013 |
| 20130312819 | REMOVAL OF STRESSOR LAYER FROM A SPALLED LAYER AND METHOD OF MAKING A BIFACIAL SOLAR CELL USING THE SAME - A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell. | 11-28-2013 |
| 20130313551 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH INTRINSIC INTERLAYERS - Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction. | 11-28-2013 |
| 20130313552 | HETEROJUNCTION BIPOLAR TRANSISTORS WITH THIN EPITAXIAL CONTACTS - Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, and/or emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. A highly doped epitaxial semiconductor layer comprising a highly doped hydrogenated crystalline semiconductor material layer portion is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. Minority carriers within the highly doped epitaxial semiconductor layer have a diffusion length that is larger than a thickness of the highly doped epitaxial semiconductor layer. | 11-28-2013 |
| 20130316488 | REMOVAL OF STRESSOR LAYER FROM A SPALLED LAYER AND METHOD OF MAKING A BIFACIAL SOLAR CELL USING THE SAME - A stressor layer used in a controlled spalling method is removed through the use of a cleave layer that can be fractured or dissolved. The cleave layer is formed between a host semiconductor substrate and the metal stressor layer. A controlled spalling process separates a relatively thin residual host substrate layer from the host substrate. Following attachment of a handle substrate to the residual substrate layer or other layers subsequently formed thereon, the cleave layer is dissolved or otherwise compromised to facilitate removal of the stressor layer. Such removal allows the fabrication of a bifacial solar cell. | 11-28-2013 |
| 20130316520 | METHODS OF FORMING CONTACT REGIONS USING SACRIFICIAL LAYERS - Methods of patterning semiconductor contact materials on a crystalline semiconductor material which allow high-quality interfaces between the crystalline semiconductor material and the patterned semiconductor contact material are provided. Blanket layers of passivation material and sacrificial material are formed on the crystalline semiconductor material. A first contact opening is formed into the blanker layer of sacrificial material. The first contact opening is extended into blanket layer of passivation material, stopping on a first surface portion of the crystalline semiconductor material, using remaining sacrificial material portions as an etch mask. A semiconductor contact material is formed on the exposed first surface portion of the crystalline semiconductor material. In some embodiments, an electrode material portion can be formed over the first contact opening, and then a second blanket layer of sacrificial material can be formed, followed by forming a next contact opening. | 11-28-2013 |
| 20130328110 | THIN FILM HYBRID JUNCTION FIELD EFFECT TRANSISTOR - Junction field effect transistors are provided which include a gate junction located on a surface of a crystalline semiconductor material of a first conductivity type. The gate junction can be selected from one of a doped hydrogenated crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, a doped hydrogenated non-crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, and a Schottky contact. | 12-12-2013 |
| 20130341623 | PHOTORECEPTOR WITH IMPROVED BLOCKING LAYER - A photoreceptor includes a multilayer blocking structure to reduce dark discharge of the surface voltage of the photoreceptor resulting from electron injection from an electrically conductive substrate. The multilayer blocking structure includes wide band gap semiconductor layers in alternating sequence with one or more narrow band gap blocking layers. A fabrication method of the photoreceptor includes transfer-doping of the narrow band gap blocking layers, which are deposited in alternating sequence with wide band gap semiconductor layers to form a blocking structure. Suppression of hole or electron injection can be obtained using the method. | 12-26-2013 |
| 20130341770 | RADIATION HARDENED SOI STRUCTURE AND METHOD OF MAKING SAME - An SOI substrate including a buried insulator layer positioned between a base substrate and a top semiconductor active layer is first provided. A semiconductor device can then be formed on and/or within a portion of the top semiconductor active layer. A bottommost surface of the buried insulator layer which is opposite a topmost surface of the buried insulator layer that forms an interface with the top semiconductor active layer can be then exposed. Ions can then be implanted through the bottommost surface of the buried insulator layer and into a portion of the buried insulator layer. The ions are implanted at energy ranges that do not disturb the buried insulator layer/top semiconductor active layer interface, while leaving a relatively thin portion of the buried insulator layer near the buried insulator layer/top semiconductor active layer interface intact. | 12-26-2013 |
| 20130344644 | PHOTORECEPTOR WITH IMPROVED BLOCKING LAYER - A photoreceptor includes a multilayer blocking structure to reduce dark discharge of the surface voltage of the photoreceptor resulting from electron injection from an electrically conductive substrate. The multilayer blocking structure includes wide band gap semiconductor layers in alternating sequence with one or more narrow band gap blocking layers. A fabrication method of the photoreceptor includes transfer-doping of the narrow band gap blocking layers, which are deposited in alternating sequence with wide band gap semiconductor layers to form a blocking structure. Suppression of hole or electron injection can be obtained using the method. | 12-26-2013 |
| 20140000687 | TEXTURED MULTI-JUNCTION SOLAR CELL AND FABRICATION METHOD | 01-02-2014 |
| 20140004654 | TEXTURED MULTI-JUNCTION SOLAR CELL AND FABRICATION METHOD | 01-02-2014 |
| 20140051190 | METHOD OF LARGE-AREA CIRCUIT LAYOUT RECOGNITION - Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce. | 02-20-2014 |
| 20140077210 | AMORPHOUS SILICON PHOTODETECTOR WITH LOW DARK CURRENT - A p-i-n photodetector includes at least one multilayer contact structure including wide gap and narrow gap layers to reduce dark current. The multilayer contact structure includes one or more wide band gap semiconductor layers in alternating sequence with one or more narrow band gap contact layers. A fabrication method of the photodetector includes transfer-doping of the narrow band gap contact layers, which are deposited in alternating sequence with wide band gap semiconductor layers. | 03-20-2014 |
| 20140252446 | EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) LOGIC AND MEMORY HYBRID CHIP - A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate. A second handle substrate may be contacted to the semiconductor on insulating layer of the transfer substrate that includes logic device. The first handle substrate may be removed to expose the dielectric layer. A memory device can then be formed on the dielectric layer. Interconnect wiring can then be formed connecting the logic device with the memory device. | 09-11-2014 |
| 20140252448 | EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) LOGIC AND MEMORY HYBRID CHIP - A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate. A second handle substrate may be contacted to the semiconductor on insulating layer of the transfer substrate that includes logic device. The first handle substrate may be removed to expose the dielectric layer. A memory device can then be formed on the dielectric layer. Interconnect wiring can then be formed connecting the logic device with the memory device. | 09-11-2014 |
| 20140367745 | T-SHAPED COMPOUND SEMICONDUCTOR LATERAL BIPOLAR TRANSISTOR ON SEMICONDUCTOR-ON-INSULATOR - A base region extends upward from a recessed semiconductor surface of a semiconductor material portion present on an insulator. The base region includes a vertical stack of, an extrinsic base region and an intrinsic base region. The extrinsic base region includes a first compound semiconductor material portion of a first conductivity type and a first dopant concentration. The intrinsic base region includes another first compound semiconductor material portion of the first conductivity type and a second dopant concentration which is less than the first dopant concentration. A collector region including a second compound semiconductor material portion of a second conductivity type opposite of the first conductivity type is located on one side on the base region. An emitter region including another second compound semiconductor material portion of the second conductivity type is located on another side on the base region. | 12-18-2014 |
| 20140370683 | T-SHAPED COMPOUND SEMICONDUCTOR LATERAL BIPOLAR TRANSISTOR ON SEMICONDUCTOR-ON-INSULATOR - A base region extends upward from a recessed semiconductor surface of a semiconductor material portion present on an insulator. The base region includes a vertical stack of, an extrinsic base region and an intrinsic base region. The extrinsic base region includes a first compound semiconductor material portion of a first conductivity type and a first dopant concentration. The intrinsic base region includes another first compound semiconductor material portion of the first conductivity type and a second dopant concentration which is less than the first dopant concentration. A collector region including a second compound semiconductor material portion of a second conductivity type opposite of the first conductivity type is located on one side on the base region. An emitter region including another second compound semiconductor material portion of the second conductivity type is located on another side on the base region. | 12-18-2014 |
