Patent application number | Description | Published |
20140310443 | Shims for Processor Interface - An interface unit configured to perform transfers between a processor and one or more peripheral devices is disclosed. A system includes a processor, a number of devices (e.g., peripheral devices), and an interface unit coupled therebetween. The interface unit includes FIFOs for storing data transmitted to or received from the devices by the processor. The interface unit may access data from a device responsive to a request from the processor. The data may be loaded into a FIFO according to transfer parameters controlled by the device. After the data has been received by the FIFO, the interface unit may generate an interrupt to the processor. Data may then be transferred from the interface unit to the processor according to transfer parameters controlled by the processor. The interface unit may thus homogenize a processor interface to a number of different devices. | 10-16-2014 |
20140310540 | Interrupt Based Power State Management - A method and apparatus for power managed interrupt handling is disclosed. In one embodiment, a system includes one or more agents that may invoke an interrupt request. An interrupt controller is configured to receive and process the interrupt requests. When idle, the interrupt controller may be placed in a low power state. The system also includes an interrupt power control circuit coupled to receive interrupt request indications from each of the one or more agents that may invoke interrupts. The interrupt power control circuit is configured to assert a wakeup signal responsive to receiving an indication of an interrupt request from one of the agents. If the interrupt controller is in a low power state, it may exit the state and resume operation in an active state responsive to assertion of the wakeup signal. | 10-16-2014 |
20140310549 | FIFO Clock and Power Management - An apparatus and method for saving power when transmitting data across a clock boundary is disclosed. In one embodiment, an apparatus includes a FIFO coupled to receive data from circuitry in a first clock domain and output data to circuitry in a second clock domain. A first control circuit is responsible for writing data into the FIFO. A second control circuit is responsible for reading data from the FIFO. If the amount of data in the FIFO exceeds a first threshold, a power management circuit may place the first control circuit in a low power state. The second control circuit may monitor the amount of data in the FIFO. If the amount of data in the FIFO falls below a second threshold, it may assert an indication to the power management circuit. Thereafter, the power management circuit may cause the first control circuit to exit the low power state. | 10-16-2014 |
20150346001 | System on a Chip with Always-On Processor - In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down. | 12-03-2015 |
20150347287 | System on a Chip with Always-On Processor Which Reconfigures SOC and Supports Memory-Only Communication Mode - In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down. | 12-03-2015 |
20150349787 | SLOW TO FAST CLOCK SYNCHRONIZATION - A method and apparatus for synchronizing data transfers from a first clock domain to a second clock domain includes sampling data from circuit included in the first clock domain. The clock signal from the first clock domain may then be synchronized to a clock signal from the second clock domain. The sampled data may then be captured using the clock signal from the second clock domain responsive to a detection of an edge of the synchronized first clock signal. | 12-03-2015 |
20160029318 | METHOD FOR WAKING A DATA TRANSCEIVER THROUGH DATA RECEPTION - A method for managing power in a system, in which the system may include a first device configured to transmit serial data and a second device, coupled to the first device. The second device may include a transceiver and interrupt logic, and may be configured to activate the interrupt logic and enable a reduced power mode for the transceiver. Power consumption of the transceiver operating in the reduced power mode may be less than power consumption of the transceiver in an operating mode. The second device may also be configured to assert an interrupt signal responsive to a change in a voltage level of an input of the second device and then de-activate the reduced power mode for the transceiver responsive to the assertion of the interrupt signal. | 01-28-2016 |
20160048191 | Subsystem Idle Aggregation - A system and method for managing idleness of functional units in an IC is disclosed. An IC includes a subsystem having a number of functional units and an idle aggregation unit. When a particular functional unit determines that it is idle, it may assert an idle indication to the idle aggregation unit. When the respective idle indications are concurrently asserted for all of the functional units, the idle aggregation unit may assert and provide respective idle request signals to each of the functional units. Responsive to receiving an idle request unit, a given functional unit may provide an acknowledgement signal to the idle aggregation unit if no transactions are incoming. If all functional units have concurrently asserted their respective acknowledgement signals, the idle aggregation unit may provide an indication of the same to a clock gating unit, which may then gate the clock signal(s) received by the functional units. | 02-18-2016 |
20160049207 | CONFIGURATION FUSE DATA MANAGEMENT IN A PARTIAL POWER-ON STATE - In an embodiment, an apparatus may include a plurality of circuit blocks, a plurality of fuses and circuitry. The circuitry may be configured to determine a state for each of the plurality of fuses in response to transitioning from an off mode to a first operating mode. A first number of circuit blocks may be enabled in the first operating mode. The circuitry may also be configured to initialize the first number of circuit blocks dependent upon the states of one or more of the plurality of fuses and to transition from the first operating mode to a second operating mode. A second number of circuit blocks, less than the first number, may be enabled in the second operating mode. The circuitry may also be configured to store data representing the states of a subset of the plurality of fuses into a first memory enabled in the second operating mode. | 02-18-2016 |
20160055110 | Transaction Filter for On-Chip Communications Network - A transaction filter for an on-chip communications network is disclosed. In one embodiment, an integrated circuit (IC) include a number of functional circuit blocks, some of which may be placed in a sleep mode (e.g., power-gated). The IC also includes a number of transaction filters that are each associated with a unique one of the functional circuit blocks. Responsive to its associated functional circuit block generating a transaction, a given transaction filter may determine whether the functional circuit block to which the transaction is destined is in a sleep mode. If it is determined that the transaction is destined for a functional circuit block that is currently in the sleep mode, the transaction filter may block the transaction from being conveyed. | 02-25-2016 |
20160077546 | METHOD FOR SYNCHRONIZING INDEPENDENT CLOCK SIGNALS - An apparatus for synchronizing two clock signals is disclosed. The apparatus may include a selection unit and circuitry. The selection unit may be configured to select a first or second clock signal as an output clock signal. A frequency of the first clock signal may be less than a frequency of the second clock signal. The circuitry may be configured to send a first signal to the selection unit, causing the selection unit to select the first clock signal. The circuitry may also be configured to send a second signal to the selection unit, causing the selection unit to select a subset of clock pulses of the second clock signal as the output clock signal. The subset of clock pulses of the second clock signal may include a clock pulse of the second clock signal corresponding to a transition of the first clock signal. | 03-17-2016 |
20160094230 | GLITCH LESS DELAY CIRCUIT FOR REAL-TIME DELAY ADJUSTMENTS - An apparatus is disclosed in which a clock signal may propagate through a delay circuit. The delay circuit may include a first and a second delay stage, in which each delay stage may be programmable for one of two delay times, depending on a value of a respective control signal to each delay stage. The delay circuit may also include circuitry which may change the value of the respective control signal from a first value to a second value. The circuitry may change the value of the respective control signal responsive to a determination that an output of the first stage and an output of the second stage are equal. | 03-31-2016 |