Patent application number | Description | Published |
20120001246 | MEMORY DEVICE AND METHOD OF FABRICATING THEREOF - Subject matter disclosed herein relates to a process flow to form a gate structure of a memory device. | 01-05-2012 |
20130087849 | METHOD OF FABRICATING A CHARGE TRAP NAND FLASH MEMORY DEVICE - Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a charge trap NAND flash memory device. | 04-11-2013 |
20130147045 | Flash Memory Having Multi-Level Architecture - Subject matter disclosed herein relates to a multi-level flash memory and a process flow to form same. | 06-13-2013 |
20140191307 | MEMORY DEVICE AND METHOD OF FABRICATING THEREOF - Subject matter disclosed herein relates to a process flow to form a gate structure of a memory device. | 07-10-2014 |
20140284812 | FORMING ARRAY CONTACTS IN SEMICONDUCTOR MEMORIES - Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts. | 09-25-2014 |
20150083986 | METHODS OF FORMING SEMICONDUCTOR DEVICES AND STRUCTURES WITH IMPROVED PLANARIZATION UNIFORMITY, AND RESULTING STRUCTURES AND SEMICONDUCTOR DEVICES - Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. Methods of forming such semiconductor devices and structures include removing memory cell material from a peripheral region and, thereafter, selectively removing portions of the memory cell material from the array region to define individual memory cells in the array region. Additional methods include planarizing the structure using peripheral conductive pads and/or spacer material over the peripheral conductive pads as a planarization stop material. Yet further methods include partially defining memory cells in the array region, thereafter forming peripheral conductive contacts, and thereafter fully defining the memory cells. | 03-26-2015 |
20150262867 | FORMING ARRAY CONTACTS IN SEMICONDUCTOR MEMORIES - Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts. | 09-17-2015 |
20150280116 | SEMICONDUCTOR STRUCTURES AND DEVICES INCLUDING CONDUCTIVE LINES AND PERIPHERAL CONDUCTIVE PADS - Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a peripheral region. An array region may include memory cells coupled to conductive lines. Methods of forming such semiconductor devices and structures include removing memory cell material from a peripheral region and, thereafter, selectively removing portions of the memory cell material from the array region to define individual memory cells in the array region. Additional methods include planarizing the structure using peripheral conductive pads and/or spacer material over the peripheral conductive pads as a planarization stop material. Yet further methods include partially defining memory cells in the array region, thereafter forming peripheral conductive contacts, and thereafter fully defining the memory cells. | 10-01-2015 |