Gogl
Dietmar Gogl, Cary, NC US
Patent application number | Description | Published |
---|---|---|
20090273966 | Integrated Circuit, Memory Cell Array, Memory Module, and Method of Operating an Integrated Circuit - According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other. | 11-05-2009 |
Dietmar Gogl, Essex Junction, VT US
Patent application number | Description | Published |
---|---|---|
20080310210 | Semiconductor memory device and method of operation - A memory cell is disclosed. The memory cell comprises a storage element including a first terminal and a second terminal, and a select transistor including a first terminal, a second terminal and a control terminal. The voltage at the control terminal of the select transistor affects a current flowing between the first terminal and the second terminal. The first terminal of the select transistor is coupled to the second terminal of the storage element. A bit line is coupled to the first terminal of the storage element, a first word line is coupled to the control terminal of the select transistor, and a second word line is coupled to the second terminal of the select transistor. | 12-18-2008 |
20090051418 | DISTRIBUTED VOLTAGE REGULATOR - An integrated circuit device and a method for providing distributed voltage regulation. The device includes a plurality of memory cell arrays and access circuitry dependent on one or more regulated voltages generated on the device and a plurality of pulsed digital distributed output units configured to generate the one or more regulated voltages. The device also includes a voltage regulator control logic configured to generate one or more control signals to control the distributed output units based, at least in part, on a comparison between one or more reference voltages and the one or more regulated voltages. | 02-26-2009 |
20090102015 | Integrated Circuit, Memory Cell Array, Memory Cell, Memory Module, Method of Operating an Integrated Circuit, and Method of Manufacturing an Integrated Circuit - According to one embodiment of the present invention, an integrated circuit includes a plurality of resistivity changing memory cells, each memory cell including a top electrode, a bottom electrode and resistivity changing material being disposed between the top electrode and the bottom electrode. The top electrodes together form a continuous common first electrode. Alternatively, a first continuous common electrode which is electrically connected to all top electrodes is disposed above the top electrodes. A second electrode connectable to a fixed potential is disposed above the first electrode such that the first electrode and the second electrode together form a capacitor. | 04-23-2009 |
Dietmar Gogl, Austin, TX US
Patent application number | Description | Published |
---|---|---|
20120155160 | MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES - A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM). | 06-21-2012 |
20130308374 | CIRCUIT AND METHOD FOR CONTROLLING MRAM CELL BIAS VOLTAGES - A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array. | 11-21-2013 |
20140104963 | MEMORY DEVICE WITH REDUCED ON-CHIP NOISE - In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device. | 04-17-2014 |
Santosh Gogl, Santa Clara, CA US
Patent application number | Description | Published |
---|---|---|
20150100890 | USER INTERFACE MANAGEMENT METHOD AND SYSTEM - A method including receiving an input associated with a user via an electronic device corresponding to the user, determining, using one or more processors operatively coupled to the electronic device, one or more personas associated with the user, the one or more personas including a first persona and a second persona, and providing, in response to the input, a first set of applications or data, or a second set of applications or data, based on a determination that the electronic device is in a mode associated with the first persona or the second persona, respectively. | 04-09-2015 |