Gunaseelan
Gunaseelan Lakshminarayanan, Shenzhen CN
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20140108672 | Content Delivery Network Routing Method, System and User Terminal - The present invention provides a content delivery network routing method, system, and user terminal. The method includes: receiving, by a CDN routing device, a first service request sent by a user terminal, where the first service request carries a first uniform resource locator URL and a domain name; returning, by the CDN routing device, a redirection response message to the user terminal, where the redirection response message carries a second URL, and the domain name; and receiving, by the cache node, a second service request sent by the user terminal, and returning a header field indication to the user terminal. Therefore, when the user terminal accesses content accelerated by a CDN, the user terminal can obtain cookie information corresponding to a domain name, which is advantageous to network-side authentication and user login information management. | 04-17-2014 |
Gunaseelan Ponnuvel, Santa Clara, CA US
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20140118021 | SYSTEM AND METHOD FOR SELECTING A DERATING FACTOR TO BALANCE USE OF COMPONENTS HAVING DISPARATE ELECTRICAL CHARACTERISTICS - A test system and method for selecting a derating factor to be applied to a ratio of transistors having disparate electrical characteristics in a wafer fabrication process. In one embodiment, the test system includes: (1) structural at-speed automated test equipment (ATE) operable to iterate structural at-speed tests at multiple clock frequencies over integrated circuit (IC) samples fabricated under different process conditions and (2) derating factor selection circuitry coupled to the structural at-speed ATE and configured to employ results of the structural at-speed tests to identify performance deterioration in the samples, the performance deterioration indicating the derating factor to be employed in a subsequent wafer fabrication process. | 05-01-2014 |
20140122005 | SYSTEM AND METHOD FOR GENERATING A YIELD FORECAST BASED ON WAFER ACCEPTANCE TESTS - A wafer acceptance test (WAT) system and method that, in one embodiment, includes: ( | 05-01-2014 |
20140125364 | SYSTEM AND METHOD FOR COMPENSATING MEASURED IDDQ VALUES - An IDDQ test system and method that, in one embodiment,deg includes 1) an empirical extraction subsystem operable to generate an IDDQ versus temperature model for a given semiconductor device design, 2) an automatic test equipment (ATE) test subsystem operable to obtain a measured IDDQ value (IDDQ | 05-08-2014 |
Gunaseelan Ponnuvel, Sunnyvale, CA US
Patent application number | Description | Published |
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20140214342 | VERIFICATION OF TEST PROGRAM STABILITY AND WAFER FABRICATION PROCESS SENSITIVITY - A system, method, and computer program product are provided for verifying sensitivity test program stability. A sensitivity test program including a set of tests is run on a plurality of integrated circuit die fabricated on a silicon wafer, where each test in the set of tests specifies a different set of operating parameters for structures within each integrated circuit die. Results of the sensitivity test program are received for each integrated circuit die and the results of the sensitivity test program are stored in shadow bins allocated within a memory, where each shadow bin corresponds to a different test in the set of tests. The results may be used to verify and optimize operating voltage and operating frequency of different tests in the production test program and wafer fabrication process sensitivity. | 07-31-2014 |