Heller, Jr.
Bernard F. Heller, Jr., Fridley, MN US
Patent application number | Description | Published |
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20100187206 | Terminal Platforms for Batteries in Implantable Medical Devices - A terminal platform comprising a first terminal block securable to a housing of the battery, a second terminal block configured to electrically connect to a terminal wire of the battery, and an insulating support electrically isolating the second terminal block from the first terminal block. | 07-29-2010 |
Bernard F. Heller, Jr., Shoreview, MN US
Patent application number | Description | Published |
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20120290021 | BATTERY FEEDTHROUGH FOR AN IMPLANTABLE MEDICAL DEVICE - A battery feedthrough comprises a ferrule having a passage extending from a first side to a second side, a pin extending through the passage, an insulation sleeve disposed between the pin and the ferrule within the passage, there being a first junction between the pin and the insulation sleeve and a second junction between the insulation sleeve and the ferrule, and a coating comprising a polymer disposed over the pin on the first side of the ferrule, wherein the coating is formed by forming a preform comprising the polymer, placing the preform around at least a first portion of the pin on the first side of the ferrule, and melting the preform so that the polymer substantially covers a second portion of the pin, the first junction, a portion of the insulation sleeve, the second junction, and a portion of the ferrule on the first side of the ferrule. | 11-15-2012 |
Bernard Frank Heller, Jr., Fridley, MI US
Patent application number | Description | Published |
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20100304212 | HERMETIC SEALING METHOD FOR A BATTERY FILLPORT USING SEALING MEMBER - A method of manufacturing an energy storage device for a medical device that includes creating an aperture in a case. The aperture includes an inner surface. The method also includes introducing an electrolyte into the case through the aperture and moving a sealing member into the aperture. The sealing member includes an outer surface. Furthermore, the method includes sealing the aperture only with the sealing member and creating a substantially hermetic seal between the inner surface of the aperture and the outer surface of the sealing member. | 12-02-2010 |
Bernard Frank Heller, Jr., Shoreview, MN US
Patent application number | Description | Published |
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20100304213 | BATTERY WITH FILLHOLE AND REDUNDANT SEAL - A method of manufacturing an energy storage device for a medical device includes enclosing a cell assembly in a case. The case includes a filling aperture. The filling aperture includes an inner surface that is integral to the case so as to be monolithic. The case is free of a separate fill port tube. Moreover, the method includes introducing an electrolyte into the case through the filling aperture and hermetically sealing the filling aperture to form a first seal of the filling aperture that is free of a filler material. The method additionally includes hermetically sealing the sealing member to the case to form a second seal of the filling aperture. | 12-02-2010 |
Thomas J. Heller, Jr., Poughkeepsie, NY US
Patent application number | Description | Published |
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20110055483 | TRANSACTIONAL MEMORY SYSTEM WITH EFFICIENT CACHE SUPPORT - A computer implemented method for use by a transaction program for managing memory access to a shared memory location for transaction data of a first thread, the shared memory location being accessible by the first thread and a second thread. A string of instructions to complete a transaction of the first thread are executed, beginning with one instruction of the string of instructions. It is determined whether the one instruction is part of an active atomic instruction group (AIG) of instructions associated with the transaction of the first thread. A cache structure and a transaction table which together provide for entries in an active mode for the AIG are located if the one instruction is part of an active AIG. The next instruction is executed under a normal execution mode in response to determining that the one instruction is not part of an active AIG. | 03-03-2011 |
20110055831 | PROGRAM EXECUTION WITH IMPROVED POWER EFFICIENCY - Program execution with improved power efficiency including a computer program that for performing a method that includes determining a current power state of a processor. Low power state instructions of an application are executed on the processor in response to determining that the current power state of the processor is a low power state. Executing the low power state instructions includes collecting hardware state data, storing the hardware state data, and performing a task. High power state instructions of the application are executed on the processor in response to determining that the current power state of the processor is a high power state. Executing the high power state instructions includes performing the task using the stored hardware state data as an input. | 03-03-2011 |
20130046937 | TRANSACTIONAL MEMORY SYSTEM WITH EFFICIENT CACHE SUPPORT - A computer implemented method for use by a transaction program for managing memory access to a shared memory location for transaction data of a first thread, the shared memory location being accessible by the first thread and a second thread. A string of instructions to complete a transaction of the first thread are executed, beginning with one instruction of the string of instructions. It is determined whether the one instruction is part of an active atomic instruction group (AIG) of instructions associated with the transaction of the first thread. A cache structure and a transaction table which together provide for entries in an active mode for the AIG are located if the one instruction is part of an active AIG. The next instruction is executed under a normal execution mode in response to determining that the one instruction is not part of an active AIG. | 02-21-2013 |
20140047186 | TRANSACTIONAL MEMORY SYSTEM WITH EFFICIENT CACHE SUPPORT - Embodiments related to a transaction program. An aspect includes, based on determining that one instruction is part of an active atomic instruction group (AIG), determining whether a private-to-transaction (PTRAN) bit associated with an address of the one instruction in a main memory is set, the PTRAN bit being located in a main memory comprising a plurality of memory increments each having a respective directly addressable PTRAN bit in the main memory. Another aspect includes, based on determining that the PTRAN bit is not set: setting the PTRAN bit; adding a new entry to a cache structure and a transaction table including an old data state of the address of the one instruction stored in the cache structure and control information stored in the transaction table; and completing the one instruction as part of the active AIG. | 02-13-2014 |