Patent application number | Description | Published |
20100138810 | PARALLELING PROCESSING METHOD, SYSTEM AND PROGRAM - Paralleling processing system and method. When clusters are formed based on strongly connected components, a single cluster (fat cluster) having at least a predetermined number of blocks, or an expected processing time exceeding a predetermined threshold, is formed. The fat cluster is subjected to an unrolling process to make multiple copies of the processing of the fat cluster and to assign the copies to individual processors. Processing of the fat cluster is executed by the multiple processor devices in a pipelined manner. If a fat cluster to be iteratively executed cannot be executed in the pipelined manner because a processing result of an n | 06-03-2010 |
20100293314 | COMPUTER SYSTEM AND METHOD OF CONTROLLING COMPUTER SYSTEM - CPU architecture is modified so that content of the interrupt mask register can be changed directly based on a decoding result of an instruction decoder of a CPU. Such modification does not require a great deal of labor in changing a CPU design. In addition, an extended CALL instruction and an extended software interrupt instruction are added to the CPU, and each of the extended CALL instruction and the extended software interrupt instruction additionally has a function of changing the value of the interrupt mask register. Atomicity is achieved by: allowing such a single instruction to concurrently execute a call of a process and a value change of the interrupt mask register; and disabling other interrupts during execution of the single instruction. | 11-18-2010 |
20110107162 | PARALLELIZATION METHOD, SYSTEM AND PROGRAM - A computer-implemented method, system, and article of manufacture for parallelizing a code configured by coupling a functional block having an internal state and a functional block without any internal state. The method includes: creating and storing a graphical representation where functional blocks are chosen as nodes and connections between functional blocks are chosen as links; visiting the nodes on the graphical representation sequentially, detecting inputs from functional blocks without any internal state to functional blocks having an internal state and storing these functional blocks as a set of use blocks, and detecting inputs from functional blocks having an internal state to functional blocks without any internal state and storing these functional blocks as a set of definition blocks; and forming strands of functional blocks based on information on the set of use blocks and information on the set of definition blocks stored in association with the functional blocks. | 05-05-2011 |
20110209129 | PARALLELIZATION METHOD, SYSTEM AND PROGRAM - A parallelization method, system and program. A program expressed by a block diagram or the like is divided into strands and a balance in calculation time is made among the strands. The functional blocks are divided into strands and the strand involving the maximum calculation time from a strand set is found. One or more movable blocks in the strand involving the maximum calculation time is found. The next step is obtaining calculation time of each strand after the movable block is moved to the strand in the input or output direction according to its property, and moving the block to a strand most largely reducing the calculation time of the strand having the maximum calculation time before the movement. This process loops until calculation time is no longer reduced. Strands are then transformed into source codes. Source codes are compiled and assigned to separate cores or processors for execution. | 08-25-2011 |
20120101791 | CONTROLLING SIMULATION SYSTEMS - A method for controlling a simulation system includes storing first-stage and second stage tables in which a value of a predicted time until arrival of an I/O instruction and a type of the instruction are included as entries for each program counter of an instruction set simulator, and in which a value of an earliest time until an output event from a peripheral simulator is included as an entry for each type of instruction; looking up the first-stage table to obtain the type of the instruction and the value of the predicted time until arrival of the instruction, looking up the second-stage table with reference to the obtained type of the instruction to obtain the value of the earliest time until the output event from the peripheral simulator, and returning the predicted time until arrival of the instruction and the earliest time until the output event from the peripheral simulator. | 04-26-2012 |
20130080609 | COMPUTER SYSTEM, METHOD, AND PROGRAM - Traffic data while the system is in operation is collected for a certain time as a preprocess. Typical patterns are extracted from the collected traffic data. Next, stream programs are created for the individual typical patterns and stored for the future reference. Next, the IDs of alternative tasks for transition among different stream programs are stored. In actual system operation, the system measures traffic data regularly or at any time, compares the resultant patterns with the typical patterns, and selects a stream program corresponding to the closest typical pattern as the next phase. Program shutdown time when shifting from the stream program in the present phase to the next phase can be reduced by gradually shifting empty tasks in the present phase to the next stream program as alternative tasks in consideration of the cost of switching between tasks, the cost of transferring data among resources, and so on. | 03-28-2013 |
20130103829 | COMPUTER SYSTEM, METHOD, AND PROGRAM - Traffic data while the system is in operation is collected for a certain time as a preprocess. Typical patterns are extracted from the collected traffic data. Next, stream programs are created for the individual typical patterns and stored for the future reference. Next, the IDs of alternative tasks for transition among different stream programs are stored. In actual system operation, the system measures traffic data regularly or at any time, compares the resultant patterns with the typical patterns, and selects a stream program corresponding to the closest typical pattern as the next phase. Program shutdown time when shifting from the stream program in the present phase to the next phase can be reduced by gradually shifting empty tasks in the present phase to the next stream program as alternative tasks in consideration of the cost of switching between tasks, the cost of transferring data among resources, and so on. | 04-25-2013 |
20140025365 | SIMULATION METHOD, SYSTEM, AND PROGRAM - System and method for achieving reproducibility of a simulation operation while reasonably keeping an operation speed. A peripheral scheduler clears completion flags of all the peripheral emulators to thereby start parallel operations thereof. Then, based on processing break timing set for the individual peripheral emulators, the peripheral scheduler finds one of the peripheral emulators which is scheduled to reach a processing break at the earliest. The found peripheral emulator is referred to as a peripheral P. In a case where a time of the processing break of the peripheral P is T, the peripheral scheduler continues execution of processor emulators and plant simulators up until a time point of the time T. The peripheral scheduler waits for setting of a completion flag of the peripheral P. In response to the setting, the peripheral scheduler performs data synchronization among the peripheral P, the processor emulators, and the plant simulators. | 01-23-2014 |