Hideko
Hideko Aoki, Tokyo JP
Patent application number | Description | Published |
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20140323201 | GAMING MACHINE AND CONTROL METHOD THEREOF - As a normal game, symbols to be rearranged on a lower image display panel | 10-30-2014 |
20140335932 | GAMING MACHINE AND CONTROL METHOD THEREOF - Symbols to be rearranged on the lower image display panel | 11-13-2014 |
20150254926 | GAMING MACHINE - Provided is a gaming machine capable of avoiding monotonousness upon executing free games in a bonus game and realizing a variety of game patterns. When a free game trigger is established, the gaming machine controls a game to shift from a basic game to the free games. In the free games, when as a result of the rearrangement of randomly determined symbols, four consecutive special symbols are rearranged in symbol display regions | 09-10-2015 |
Hideko Fukushima, Yasugi JP
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20100330738 | Oxide semiconductor target and manufacturing method of oxide semiconductor device by using the same - An oxide semiconductor target of a ZTO (zinc tin complex oxide) type oxide semiconductor material of an appropriate (Zn/(Zn+Sn)) composition having high mobility and threshold potential stability and with less restriction in view of the cost and the resource and with less restriction in view of the process, and an oxide semiconductor device using the same, in which a sintered Zn tin complex oxide with a (Zn/(Zn+Sn)) composition of 0.6 to 0.8 is used as a target, the resistivity of the target itself is at a high resistance of 1 Ωcm or higher and, further, the total concentration of impurities is controlled to 100 ppm or less. | 12-30-2010 |
20150321247 | CERAMIC CORE AND METHOD FOR PRODUCING SAME - A ceramic core is obtained by firing a mixture that contains 0.1-15.0% by mass of alumina and 0.005-0.1% by mass of potassium and/or sodium with the balance made up of silica and unavoidable impurities. Not less than 90% by mass of amorphous silica is contained in 100% by mass of the silica. A method for producing a ceramic core, wherein: a blended material is obtained by blending 25-45% by volume of a binder into 55-75% by volume of a mixture that is obtained by mixing alumina, potassium and/or sodium, and silica so as to have the above-mentioned composition; the blended material is injected into a die so as to obtain a molded body; and the molded body is degreased at 500-600° C. for 1-10 hours, and then fired at 1,200-1,400° C. for 1-10 hours. | 11-12-2015 |
Hideko Fukushima, Saitama-Ken JP
Patent application number | Description | Published |
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20090035562 | HIGH-THERMAL-CONDUCTIVITY GRAPHITE-PARTICLES-DISPERSED-COMPOSITE AND ITS PRODUCTION METHOD - A graphite-particles-dispersed composite produced by compacting graphite particles coated with a high-thermal-conductivity metal such as silver, copper and aluminum, the graphite particles having an average particle size of 20-500 μm, the volume ratio of the graphite particles to the metal being 60/40-95/5, and the composite having thermal conductivity of 150 W/mK or more in at least one direction. | 02-05-2009 |
20110086218 | COMPOSITE MATERIAL, HAVING HIGH THERMAL CONDUCTIVITY AND LOW THERMAL EXPANSION COEFFICIENT, AND HEAT-DISSIPATING SUBSTRATE, AND THEIR PRODUCTION METHODS - A composite material having a high thermal conductivity and a small thermal expansion coefficient, which is obtained by impregnating a porous graphitized extrudate with a metal; the composite material having such anisotropy that the thermal conductivity and the thermal expansion coefficient are 250 W/mK a more and less than 4×10 | 04-14-2011 |
Hideko Fukushima, Tokyo JP
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20140042431 | OXIDE SEMICONDUCTOR TARGET AND OXIDE SEMICONDUCTOR MATERIAL, AS WELL AS SEMICONDUCTOR DEVICE USING THE SAME - There are provided an oxide semiconductor material, capable of attaining stability of a threshold voltage (Vth) (threshold voltage shift amount ΔVth within a range of ±3 V in PDS and NBIS) and field-effect mobility of 5 cm | 02-13-2014 |
Hideko Fukushima, Shimane JP
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20150072163 | CERAMIC CORE, MANUFACTURING METHOD FOR THE SAME, MANUFACTURING METHOD FOR CASTING USING THE CERAMIC CORE, AND CASTING MANUFACTURED BY THE METHOD - A ceramic core includes sintered ceramic powder and a hole opening on a surface of the ceramic core and having an opening portion with a maximum size of 100 μm or less. | 03-12-2015 |
Hideko Fukushima, Yasugi-Shi, Shimane JP
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20160035895 | OXIDE SEMICONDUCTOR TARGET, OXIDE SEMICONDUCTOR FILM AND METHOD FOR PRODUCING SAME, AND THIN FILM TRANSISTOR - The invention provides an oxide semiconductor target including an oxide sintered body including zinc, tin, oxygen, and aluminum in a content ratio of from 0.005% by mass to 0.2% by mass with respect to the total mass of the oxide sintered body, in which the content ratio of silicon to the total mass of the oxide sintered body is less than 0.03% by mass. | 02-04-2016 |
Hideko Inoue, Atsugl JP
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20110082296 | Organometallic Complex, and Light-Emitting Element, Light-Emitting Device, Electronic Device and Electronic Device Using the Organometallic Complex - An object is to provide a novel organometallic complex capable of emitting phosphorescence, an organometallic complex which exhibits deep red emission, and a light-emitting element which provides deep red emission. Provided is an organometallic complex having a structure represented by the following General Formula (G1). | 04-07-2011 |
Hideko Iwamoto, Nishitama JP
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20150205436 | Electronic Apparatus and Control Method of Electronic Apparatus - An electronic apparatus includes a display, a touch panel, an input receiving module and a threshold value correcting module. The touch panel is configured to be superimposed on the display. The input receiving module is configured to receive an input through the touch panel. The threshold value correcting module is configured to correct a threshold value which determines whether or not a touch is input. | 07-23-2015 |
Hideko Kitamura, Atsugi-Shi JP
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20130015692 | ARMRESTAANM Saito; MakotoAACI Ina-ShiAACO JPAAGP Saito; Makoto Ina-Shi JPAANM Morimoto; TakashiAACI Ina-ShiAACO JPAAGP Morimoto; Takashi Ina-Shi JPAANM Suzuki; KenAACI Aiko-gunAACO JPAAGP Suzuki; Ken Aiko-gun JPAANM Numazawa; ToshikazuAACI Aiko-gunAACO JPAAGP Numazawa; Toshikazu Aiko-gun JPAANM Kitamura; HidekoAACI Atsugi-shiAACO JPAAGP Kitamura; Hideko Atsugi-shi JP - An armrest includes a stationary shaft, fixed to a seat frame, the shaft is inserted and is rotatable about an armrest body, a spring wound around the shaft, one end of the spring being a stationary-side hook locked to the armrest, the other spring end being a free-side hook, a hook-supporting part supporting the free-side hook in a raised direction of the shaft, a hook-joint enlarging a spring diameter by dropping the free-side hook on the hook-supporting part downward in the axial direction of the shaft, and a cam on the shaft | 01-17-2013 |
Hideko Murakami, Yokohama-Shi, Kanagawa JP
Patent application number | Description | Published |
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20160057280 | MOBILE ELECTRONIC DEVICE, CONTROL METHOD, AND CONTROL PROGRAM - In one aspect, a mobile electronic device includes a sound input module and a controller for performing off-hook when sound input to the sound input module is accepted at a time of incoming call. The mobile electronic device performs off-hook when a response operation to the incoming call is detected through a touch screen, starts to accept sound input through the sound input module when a response operation to the incoming call is not detected through the touch screen, and performs off-hook when the sound input is accepted. | 02-25-2016 |
20160077702 | DEVICE, METHOD, AND PROGRAM - A device, includes: a touch screen display; and a controller configured to, when the touch screen display detects that a physical body has moved in a predetermined direction while contacting with the touch screen display, cause an object on which a text is inputtable to be displayed on a screen displayed on the touch screen display along a trajectory of the moving. | 03-17-2016 |
Hideko Oodaira, Kuroishi-Shi JP
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20100309722 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REALIZING A CHIP WITH HIGH OPERATION RELIABILITY AND HIGH YIELD - A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder. | 12-09-2010 |
20100309723 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REALIZING A CHIP WITH HIGH OPERATION RELIABILITY AND HIGH YIELD - A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder. | 12-09-2010 |
20110134700 | Nonvolatile Semiconductor Memory - A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode. | 06-09-2011 |
20120075903 | Nonvolatile Semiconductor Memory - A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode. | 03-29-2012 |
20120314497 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REALIZING A CHIP WITH HIGH OPERATION RELIABILITY AND HIGH YIELD - A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder. | 12-13-2012 |