Patent application number | Description | Published |
20090014765 | High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof - A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconductor channel formation region is disposed in the surface of the substrate between the source region and the drain region. A gate region is disposed above the channel formation region and is operative to receive a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential. A gate insulating film region is disposed between the channel formation region and the gate region. | 01-15-2009 |
20090014816 | High voltage operating field effect transistor, and bias circuit therefor and high voltage circuit thereof - A high voltage operating field effect transistor has a substrate and a semiconductor channel formation region disposed in a surface of the substrate. A source region and a drain region are spaced apart from each other with the semiconductor channel formation region disposed between the source region and the drain region. A gate insulating film region is disposed on the semiconductor channel formation region. A resistive gate region is disposed on the gate insulating film region. A source side electrode is disposed on a source region side of the resistive gate region and is operative to receive a signal electric potential. A drain side electrode is disposed on a drain region side of the resistive gate region and is operative to receive a bias electric potential an absolute value of which is equal to or larger than that of a specified electric potential and which changes according to an increase or decrease in a drain electric potential. | 01-15-2009 |
20090101973 | Field effect transistor formed on an insulating substrate and integrated circuit thereof - A field effect transistor has an insulating substrate, a semiconductor thin film formed on the insulating substrate, and a gate insulating film on the semiconductor thin film. A first gate electrode is formed on the gate insulating film. A first region and a second region having a first conductivity type are formed on or in a surface of the semiconductor film on opposite sides of the first gate electrode in a length direction thereof. A third region having a second conductivity type opposite the first conductivity type is arranged on or in the semiconductor film side by side with the second region in a width direction of the first gate electrode. The third region and the second region are in contact with each other and make a low resistance junction. A second gate electrode is formed on the gate insulating film along the second region. A fourth region having the first conductivity type is formed on or in the semiconductor film on an opposite side of the second region with respect to the second gate electrode. One of the first and the fourth regions is used as an output region according to a circuit operation. | 04-23-2009 |
20090283864 | Semiconductor device - In order to reduce a device area, a bipolar transistor using temperature characteristics of a forward voltage generated between an emitter and a base has a structure in which a high concentration second conductivity type impurity region for a base electrode and a high concentration first conductivity type impurity region for a collector electrode are brought into direct contact with each other to prevent formation of an unnecessary isolation region. Further, an emitter region is disposed to self-align with a device isolation insulating film or a polycrystalline silicon arranged on a surface of a semiconductor substrate. | 11-19-2009 |
20100224933 | Semiconductor device - Provided is a semiconductor device including an N-channel high-voltage MOS transistor, in which wiring metal connected to a drain region is laid above a boundary portion between an oxide film formed by LOCOS process or the like on a low impurity concentration region and a high impurity concentration region forming the drain region, to thereby alleviate an electric field concentration at the boundary portion which is a contact portion between the low impurity concentration region and the high impurity concentration region by an electric field generated from the wiring metal toward a semiconductor substrate. | 09-09-2010 |
20110027949 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device formed to an SOI substrate including a MOS transistor in which a parasitic MOS transistor is suppressed. The semiconductor device formed on the SOI substrate by employing a LOCOS process is structured such that a part of a polysilicon layer to becomes a gate electrode includes: a first conductivity type polysilicon region corresponding to a region of the silicon active layer which has a constant thickness and is to become a channel; and second conductivity type polysilicon regions corresponding to LOCOS isolation edges in each of which a thickness of the silicon active layer decreases. | 02-03-2011 |