Patent application number | Description | Published |
20110072405 | Chip-Level ECO Shrink - In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed. | 03-24-2011 |
20120226479 | Method of Generating RC Technology File - A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure. | 09-06-2012 |
20130014070 | SYSTEMS AND METHODS FOR CREATING FREQUENCY-DEPENDENT NETLIST - A method includes creating a technology file including data for an integrated circuit including at least one die coupled to an interposer and a routing between the at least one die and the interposer, b) creating a netlist including data approximating at least one of capacitive or inductive couplings between conductors in the at least one die and in the interposer based on the technology file, c) simulating a performance of the integrated circuit based on the netlist, d) adjusting the routing between the at least one die and the interposer based on the simulation to reduce the at least one of the capacitive or the inductive couplings, and e) repeating steps c) and d) to optimize the at least one of the capacitive or inductive couplings. | 01-10-2013 |
20130061186 | MULTI-PATTERNING METHOD - A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks. | 03-07-2013 |
20130074018 | MULTI-PATTERNING METHOD - A method comprises (a) receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool, the layout including a plurality of polygons to be formed in the DPT-layer by a multi-patterning process; (b) receiving at least one identification of a subset of the plurality of polygons that are to be formed in the DPT-layer using the same photomask as each other; (c) constructing a graph of the subset of the plurality of polygons and any intervening polygons of the plurality of polygons, where the subset of the plurality of polygons are represented in the graph by a single node, the graph including connections connecting adjacent ones of the polygons in the graph that are positioned within a threshold distance of each other; and (d) identifying a multi-patterning conflict if any subset of the connections form an odd loop. | 03-21-2013 |
20130139121 | RC Extraction Methodology for Floating Silicon Substrate with TSV - The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows. | 05-30-2013 |
20130174112 | METHOD OF GENERATING A BIAS-ADJUSTED LAYOUT DESIGN OF A CONDUCTIVE FEATURE AND METHOD OF GENERATING A SIMULATION MODEL OF A PREDEFINED FABRICATION PROCESS - A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule. | 07-04-2013 |
20130227501 | SEMICONDUCTOR DEVICE DESIGN METHOD, SYSTEM AND COMPUTER-READABLE MEDIUM - In a semiconductor device design method performed by at least one processor, first and second electrical components are extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second electrical components in the semiconductor substrate. Parasitic parameters of a coupling in the semiconductor substrate between the first and second electrical components are extracted using a first tool. Intrinsic parameters of the first and second electrical components are extracted using a second tool different from the first tool. The extracted parasitic parameters and intrinsic parameters are combined into a model of the semiconductor device. The parasitic parameters of the coupling are extracted based on a model of the coupling included in the second tool. | 08-29-2013 |
20130227514 | Method of Generating RC Technology File - A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure. | 08-29-2013 |
20130239070 | RC EXTRACTION FOR SINGLE PATTERNING SPACER TECHNIQUE - A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns. | 09-12-2013 |
20130254726 | MULTI-PATTERNING METHOD - A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks. | 09-26-2013 |
20130275927 | RC Corner Solutions for Double Patterning Technology - A method includes determining model parameters for forming an integrated circuit, and generating a techfile using the model parameters. The techfile includes at least two of a C_worst table, a C_best table, and a C_nominal table. The C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other. The C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. The techfile is embodied on a tangible non-transitory storage medium. | 10-17-2013 |
20140082578 | RC EXTRACTION METHODOLOGY FOR FLOATING SILICON SUBSTRATE WITH TSV - The present disclosure relates to methods and apparatuses for generating a through-silicon via (TSV) model for RC extraction that accurately models an interposer substrate comprising one or more TSVs. In some embodiments, a method is performed by generating an interposer wafer model having a sub-circuit that models a TSV. The sub-circuit can compensate for limitations in resistive and capacitive extraction of traditional TSV models performed by EDA tools. In some embodiments, the sub-circuit is coupled to a floating common node of the model. The floating common node enables the interposer wafer model to take into consideration capacitive coupling within the interposer. The improved interposer wafer model enables accurate RC extraction of an interposer with one or more TSVs, thereby providing for an interposer wafer model that is consistent between GDS and APR flows. | 03-20-2014 |
20140245251 | Design Optimization for Circuit Migration - An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist. | 08-28-2014 |
20140258962 | Parasitic Capacitance Extraction for FinFETs - A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings of the FinFETs, fin-to-fin spacings of the FinFETs, and metal-contact-to-second-poly spacings of the FinFETs. The step of generating the three-dimensional table is performed using a computer. | 09-11-2014 |
20140304670 | RC Corner Solutions for Double Patterning Technology - A method includes selecting a process corner, determining model parameters for forming an integrated circuit, and generating a file using the model parameters for the process corner. The generating the file is performed using a computer. The file includes at least two of a first capacitance table, a second capacitance table, and a third capacitance table. The first capacitance table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks including the layout patterns shift relative to each other. The second capacitance table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The third capacitance table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. | 10-09-2014 |
20140310675 | Methods and Apparatus for RC Extraction - The method for extracting a capacitance from a layout is disclosed. The method decomposes a first net into a first and a second component, and decomposes a second net into a third and a fourth component. The method may obtain a first capacitance for the first component and the third component by a first method, and obtain a second capacitance for the second component and the fourth component by a second method different from the first method. A library with a plurality of entries may be provided, wherein each entry has a component pair comprising a component of the first net and a component of the second net, and a pre-calculated capacitance for the component pair. The first method may be to search a library to find a pre-calculated capacitance. The second method may be to obtain the first capacitance by an equation solver on the fly. | 10-16-2014 |
20150052493 | METHOD OF GENERATING A SIMULATION MODEL OF A PREDEFINED FABRICATION PROCESS - A method of generating a simulation model of a predefined fabrication process according to a sample conductive feature includes receiving a geometry configuration and layout design of the conductive feature. A circuit-level simulation model of the sample conductive feature based on the geometry configuration of the sample conductive feature is generated. A hardware processor converts the circuit-level simulation model of the sample conductive feature into at least a first layout bias rule corresponding to a first set of predetermined criteria of the layout design and a second layout bias rule, different from the first layout bias rule, corresponding to a second set of predetermined criteria of the layout design. | 02-19-2015 |