Patent application number | Description | Published |
20080217144 | Impact sensing switch - An impact switch includes a housing having a wall including at least two electrically conductive contact elements spaced apart from one another. The switch includes an inertial body having a conductive surface disposed in a tapered aperture and electrically connecting the contact elements to one another in a switch closed condition. An impact switch for rapidly firing an explosive device is provided. | 09-11-2008 |
20080254825 | Wearable ultra-thin miniaturized mobile communications - A cellular telephone is provided with a wearable housing, desirably in a form which can be concealed in the user's clothing, wallet, or other place. The housing may be devoid of switches or buttons for controlling the cellular telephone, and control inputs can be provided through free space communications such as a short-range radio link. A module for use in portable communications devices includes chips superposed on one another on a stack, and incorporates an interposer for facilitating connections between the chips. | 10-16-2008 |
20080296749 | Package stacking through rotation - A packaged microelectronic element includes a package element that further includes a dielectric element having a bottom face and a top face, first and second bond windows extending between the top and bottom faces, a plurality of chip contacts disposed at the top face adjacent to the first and second bond windows, and first and second sets of package contacts exposed at diagonally opposite corner regions of the top face, wherein the first and second sets conductively connected to the chip contacts. There is also a microelectronic element adjacent to the bottom face of the dielectric element, as well as bond wires extending through the first and second bond windows to conductively connect the microelectronic element to the chip contacts. | 12-04-2008 |
20080303132 | Semiconductor chip packages having cavities - Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts. | 12-11-2008 |
20090039528 | Wafer level stacked packages with individual chip selection - A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like microelectronic elements attached together at dicing lanes. Each microelectronic element has boundaries defined by edges including a first edge and a second edge. The first and second microelectronic substrates can be joined in different orientations, such that first edges of microelectronic elements of the first microelectronic substrate are aligned with second edges of microelectronic elements of the second microelectronic substrate. After exposing traces at the first and second edges of the microelectronic elements of the stacked microelectronic substrates, first and second leads can be formed which are connected to the exposed traces of the first and second microelectronic substrates, respectively. The second leads can be electrically isolated from the first leads. | 02-12-2009 |
20090316378 | Wafer level edge stacking - A microelectronic assembly can include a first microelectronic device and a second microelectronic device. Each microelectronic device has a die structure including at least one semiconductor die and each of the microelectronic devices has a first surface, a second surface remote from the first surface and at least one edge surface extending at angles other than a right angle away from the first and second surfaces. At least one electrically conductive element extends along the first surface onto at least one of the edge surfaces and onto the second surface. At least one conductive element of the first microelectronic device can be conductively bonded to the at least one conductive element of the second microelectronic device to provide an electrically conductive path therebetween. | 12-24-2009 |
20100232129 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A method of making a microelectronic assembly includes providing a microelectronic package having a substrate, a microelectronic element overlying the substrate and at least two conductive elements projecting from a surface of the substrate, the at least two conductive elements having surfaces remote from the surface of the substrate. The method includes compressing the at least two conductive elements so that the remote surfaces thereof lie in a common plane, and after the compressing step, providing an encapsulant material around the at least two conductive elements for supporting the microelectronic package and so that the remote surfaces of the at least two conductive elements remain accessible at an exterior surface of the encapsulant material. | 09-16-2010 |
20100258956 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package. | 10-14-2010 |
20110049696 | OFF-CHIP VIAS IN STACKED CHIPS - A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements. | 03-03-2011 |
20110165733 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A method of making a microelectronic assembly can include molding a dielectric material around at least two conductive elements which project above a height of a substrate having a microelectronic element mounted thereon, so that remote surfaces of the conductive elements remain accessible and exposed within openings extending from an exterior surface of the molded dielectric material. The remote surfaces can be disposed at heights from said surface of said substrate which are lower or higher than a height of the exterior surface of the molded dielectric material from the substrate surface. The conductive elements can be arranged to simultaneously carry first and second different electric potentials: e.g., power, ground or signal potentials. | 07-07-2011 |
20110269272 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package. | 11-03-2011 |
20110291296 | PACKAGE STACKING THROUGH ROTATION - A packaged microelectronic element includes a package element that further includes a dielectric element having a bottom face and a top face, first and second bond windows extending between the top and bottom faces, a plurality of chip contacts disposed at the top face adjacent to the first and second bond windows, and first and second sets of package contacts exposed at diagonally opposite corner regions of the top face, wherein the first and second sets conductively connected to the chip contacts. There is also a microelectronic element adjacent to the bottom face of the dielectric element, as well as bond wires extending through the first and second bond windows to conductively connect the microelectronic element to the chip contacts. | 12-01-2011 |
20110291297 | MICROELECTRONIC PACKAGES HAVING CAVITIES FOR RECEIVING MICROELECTRONIC ELEMENTS - Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts. | 12-01-2011 |
20120013028 | STACKED MICROELECTRONIC PACKAGES HAVING AT LEAST TWO STACKED MICROELECTRONIC ELEMENTS ADJACENT ONE ANOTHER - A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element. | 01-19-2012 |
20120018863 | MICROELECTRONIC ELEMENTS WITH REAR CONTACTS CONNECTED WITH VIA FIRST OR VIA MIDDLE STRUCTURES - A microelectronic unit includes a microelectronic element, e.g., an integrated circuit chip, having a semiconductor region of monocrystalline form. The semiconductor region has a front surface extending in a first direction, an active circuit element adjacent the front surface, a rear surface remote from the front surface, and a conductive via which extends towards the rear surface. The conductive via can be insulated from the semiconductor region by an inorganic dielectric layer. An opening can extend from the rear surface partially through a thickness of the semiconductor region, with the opening and the conductive via having respective widths in the first direction. The width of the opening may be greater than the width of the conductive via where the opening meets the conductive via. A rear contact can be electrically connected to the conductive via and exposed at the rear surface for electrical connection with an external circuit element, such as another like microelectronic unit, a microelectronic package, or a circuit panel. | 01-26-2012 |
20120018868 | MICROELECTRONIC ELEMENTS HAVING METALLIC PADS OVERLYING VIAS - A microelectronic unit, an interconnection substrate, and a method of fabricating a microelectronic unit are disclosed. A microelectronic unit can include a semiconductor element having a plurality of active semiconductor devices therein, the semiconductor element having a first opening extending from a rear surface partially through the semiconductor element towards a front surface and at least one second opening, and a dielectric region overlying a surface of the semiconductor element in the first opening. The microelectronic unit can include at least one conductive interconnect electrically connected to a respective conductive via and extending away therefrom within the aperture. In a particular embodiment, at least one conductive interconnect can extend within the first opening and at least one second opening, the conductive interconnect being electrically connected with a conductive pad having a top surface exposed at the front surface of the semiconductor element. | 01-26-2012 |
20120018893 | METHODS OF FORMING SEMICONDUCTOR ELEMENTS USING MICRO-ABRASIVE PARTICLE STREAM - A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device. | 01-26-2012 |
20120018894 | NON-LITHOGRAPHIC FORMATION OF THREE-DIMENSIONAL CONDUCTIVE ELEMENTS - A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate. | 01-26-2012 |
20120018895 | ACTIVE CHIP ON CARRIER OR LAMINATED CHIP HAVING MICROELECTRONIC ELEMENT EMBEDDED THEREIN - A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity. | 01-26-2012 |
20120020026 | MICROELECTRONIC ELEMENTS WITH POST-ASSEMBLY PLANARIZATION - A microelectronic unit includes a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can include a microelectronic element having a bottom surface adjacent the inner surface, a top surface remote from the bottom surface, and a plurality of contacts at the top surface. The microelectronic element can include terminals electrically connected with the contacts of the microelectronic element. The microelectronic unit can include a dielectric region contacting at least the top surface of the microelectronic element. The dielectric region can have a planar surface located coplanar with or above the front surface of the carrier structure. The terminals can be exposed at the surface of the dielectric region for interconnection with an external element. | 01-26-2012 |
20120032349 | METHOD OF FABRICATING STACKED ASSEMBLY INCLUDING PLURALITY OF STACKED MICROELECTRONIC ELEMENTS - A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like microelectronic elements attached together at dicing lanes. Each microelectronic element has boundaries defined by edges including a first edge and a second edge. The first and second microelectronic substrates can be joined in different orientations, such that first edges of microelectronic elements of the first microelectronic substrate are aligned with second edges of microelectronic elements of the second microelectronic substrate. After exposing traces at the first and second edges of the microelectronic elements of the stacked microelectronic substrates, first and second leads can be formed which are connected to the exposed traces of the first and second microelectronic substrates, respectively. The second leads can be electrically isolated from the first leads. | 02-09-2012 |
20120068327 | MULTI-FUNCTION AND SHIELDED 3D INTERCONNECTS - A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element. | 03-22-2012 |
20120068330 | STAGED VIA FORMATION FROM BOTH SIDES OF CHIP - A method of fabricating a semiconductor assembly can include providing a semiconductor element having a front surface, a rear surface, and a plurality of conductive pads, forming at least one hole extending at least through a respective one of the conductive pads by processing applied to the respective conductive pad from above the front surface, forming an opening extending from the rear surface at least partially through a thickness of the semiconductor element, such that the at least one hole and the opening meet at a location between the front and rear surfaces, and forming at least one conductive element exposed at the rear surface for electrical connection to an external device, the at least one conductive element extending within the at least one hole and at least into the opening, the conductive element being electrically connected with the respective conductive pad. | 03-22-2012 |
20120068351 | CHIP ASSEMBLY HAVING VIA INTERCONNECTS JOINED BY PLATING - An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element. | 03-22-2012 |
20120068352 | STACKED CHIP ASSEMBLY HAVING VERTICAL VIAS - An assembly and method of making same are provided. The assembly can be formed by stacking a first semiconductor element atop a second semiconductor element and forming an electrically conductive element extending through openings of the semiconductor elements. The openings may be staged. The conductive element can conform to contours of the interior surfaces of the openings and can electrically connect conductive pads of the semiconductor elements. A dielectric region can be provided at least substantially filling the openings of the semiconductor elements, and the electrically conductive element can extend through an opening formed in the dielectric region. | 03-22-2012 |
20120080807 | OFF-CHIP VIAS IN STACKED CHIPS - A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements. | 04-05-2012 |
20120104595 | NO FLOW UNDERFILL - A method for making a microelectronic assembly includes providing a microelectronic element with first conductive elements and a dielectric element with second conductive elements. At least some of either the first conductive elements or the second conductive elements may be conductive posts and other of the first or second conductive elements may include a bond metal disposed between some of the conductive posts. An underfill layer may overly some of the first or second conductive elements. At least one of the first conductive elements may be moved towards the other of the second conductive elements so that the posts pierce the underfill layer and at least deform the bond metal. The microelectronic element and the dielectric element can be heated to join them together. The height of the posts above the surface may be at least forty percent of a distance between surfaces of the microelectronic element and dielectric element. | 05-03-2012 |
20120139082 | STACKED MICROELECTRONIC ASSEMBY WITH TSVS FORMED IN STAGES AND CARRIER ABOVE CHIP - A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element. A conductive element extends within the first and second openings and contacts the at least one conductive pad. | 06-07-2012 |
20120139094 | STACKED MICROELECTRONIC ASSEMBLY HAVING INTERPOSER CONNECTING ACTIVE CHIPS - A microelectronic assembly can include first and second microelectronic elements each embodying active semiconductor devices adjacent a front surface thereof, and having an electrically conductive pad exposed at the respective front surface. An interposer of material having a CTE less than 10 ppm/° C. has first and second surfaces attached to the front surfaces of the respective first and second microelectronic elements, the interposer having a second conductive element extending within an opening in the interposer. First and second conductive elements extend within openings extending from the rear surface of a respective microelectronic element of the first and second microelectronic elements towards the front surface of the respective microelectronic element. In one example, one or more of the first or second conductive elements extends through the respective first or second pad, and the conductive elements contact the exposed portions of the second conductive element to provide electrical connection therewith. | 06-07-2012 |
20120139124 | STACKED MICROELECTRONIC ASSEMBLY WITH TSVS FORMED IN STAGES WITH PLURAL ACTIVE CHIPS - A microelectronic assembly is provided in which first and second electrically conductive pads exposed at front surfaces of first and second microelectronic elements, respectively, are juxtaposed, each of the microelectronic elements embodying active semiconductor devices. An electrically conductive element may extend within a first opening extending from a rear surface of the first microelectronic element towards the front surface thereof, within a second opening extending from the first opening towards the front surface of the first microelectronic element, and within a third opening extending through at least one of the first and second pads to contact the first and second pads. Interior surfaces of the first and second openings may extend in first and second directions relative to the front surface of the first microelectronic element, respectively, to define a substantial angle. | 06-07-2012 |
20120145442 | INTERCONNECT STRUCTURE - A microelectronic assembly includes a first surface and a first thin conductive element exposed at the first surface and having a face comprising first and second regions. A first conductive projection having a base connected to and covering the first region of the face extends to an end remote from the base. A first dielectric material layer covers the second region of the first thin element and contacts at least the base of the first conductive projection. The assembly further includes a second substrate having a second face and a second conductive projection extending away from the second face. A first fusible metal mass connects the first projection to the second projection and extends along an edge of the first projection towards the first dielectric material layer. | 06-14-2012 |
20120146182 | HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS - A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates. | 06-14-2012 |
20120146206 | PIN ATTACHMENT - A microelectronic package includes a substrate having a first region, a second region, a first surface, and a second surface remote from the first surface. At least one microelectronic element overlies the first region on the first surface. First electrically conductive elements are exposed at one of the first surface and the second surface of the substrate within the second region with at least some of the first conductive elements electrically connected to the at least one microelectronic element. Substantially rigid metal elements overlie the first conductive elements and have end surfaces remote therefrom. A bond metal joins the metal elements with the first conductive elements, and a molded dielectric layer overlies at least the second region of the substrate and has a surface remote from the substrate. The end surfaces of the metal elements are at least partially exposed at the surface of the molded dielectric layer. | 06-14-2012 |
20120146210 | COMPLIANT INTERCONNECTS IN WAFERS - A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit. | 06-14-2012 |
20120152433 | DUAL WAFER SPIN COATING - A method of bonding a first substrate and a second substrate includes the steps of rotating first substrate with an adhesive mass thereon, and second substrate contacting the mass and overlying the first substrate, controlling a vertical height of a heated control platen spaced apart from and not contacting the second substrate so as to control a temperature of the adhesive mass, so as to at least one of bond the first and second substrates in alignment with one another, or achieve a sufficiently planar adhesive interface between the first and second substrates. | 06-21-2012 |
20120153426 | VOID-FREE WAFER BONDING USING CHANNELS - A method of bonding first and second microelectronic elements includes pressing together a first substrate containing active circuit elements therein with a second substrate, with a flowable dielectric material between confronting surfaces of the respective substrates, each of the first and second substrates having a coefficient of thermal expansion less than 10 parts per million/° C., at least one of the confronting surfaces having a plurality of channels extending from an edge of such surface, such that the dielectric material between planes defined by the confronting surfaces is at least substantially free of voids and has a thickness over one micron, and at least some of the dielectric material flows into at least some of the channels. | 06-21-2012 |
20120153488 | SIMULTANEOUS WAFER BONDING AND INTERCONNECT JOINING - Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip. | 06-21-2012 |
20120155055 | SEMICONDUCTOR CHIP ASSEMBLY AND METHOD FOR MAKING SAME - A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly. | 06-21-2012 |
20120181658 | HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS - A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape. | 07-19-2012 |
20120196650 | WEARABLE ULTRA-THIN MINIATURIZED MOBILE COMMUNICATIONS - A cellular telephone is provided with a wearable housing, desirably in a form which can be concealed in the user's clothing, wallet, or other place. The housing may be devoid of switches or buttons for controlling the cellular telephone, and control inputs can be provided through free space communications such as a short-range radio link. A module for use in portable communications devices includes chips superposed on one another on a stack, and incorporates an interposer for facilitating connections between the chips. | 08-02-2012 |
20120199924 | BSI IMAGE SENSOR PACKAGE WITH VARIABLE LIGHT TRANSMISSION FOR EVEN RECEPTION OF DIFFERENT WAVELENGTHS - A microelectronic image sensor assembly for backside illumination and method of making same are provided. The assembly includes a microelectronic element having contacts exposed at a front face and light sensing elements arranged to receive light of different wavelengths through a semiconductor region adjacent a rear face. The semiconductor region has a first region of material overlying the first light sensing element and a second region of material overlying the second light sensing element such that the first and second wavelengths are able to pass through the first and second regions, respectively, and reach the first and second light sensing elements with substantially the same intensity. | 08-09-2012 |
20120199925 | BSI IMAGE SENSOR PACKAGE WITH EMBEDDED ABSORBER FOR EVEN RECEPTION OF DIFFERENT WAVELENGTHS - A microelectronic image sensor assembly for backside illumination and method of making same are provided. The assembly includes a microelectronic element having contacts exposed at a front face and light sensing elements arranged to receive light of different wavelengths through a rear face. A semiconductor region has an opening overlying at least one of first and second light sensing elements, the semiconductor region having a first thickness between the first light sensing element and the rear face and a second thickness between the second light sensing element and the rear face. A light-absorbing material overlies the semiconductor region within the opening above at least one of the light sensing elements such that the first and second light sensing elements receive light of substantially the same intensity. | 08-09-2012 |
20120199926 | BSI IMAGE SENSOR PACKAGE WITH VARIABLE-HEIGHT SILICON FOR EVEN RECEPTION OF DIFFERENT WAVELENGTHS - A microelectronic image sensor assembly for backside illumination and method of making same are provided. The assembly includes a microelectronic element having contacts exposed at a front face and light sensing elements arranged to receive light of different wavelengths through a rear face. A semiconductor region has a first thickness between the first light sensing element and the rear face and a second thickness between the second light sensing element and the rear face such that the first and second light sensing elements receive light of substantially the same intensity. A dielectric region is provided at least substantially filling a space of the semiconductor region adjacent at least one of the light sensing elements. The dielectric region may include at least one light guide. | 08-09-2012 |
20120267751 | INTERPOSER HAVING MOLDED LOW CTE DIELECTRIC - A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel. | 10-25-2012 |
20120267777 | MULTI-CHIP MODULE WITH STACKED FACE-DOWN CONNECTED DIES - A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component. Signal contacts of each logic chip can be directly electrically connected to signal contacts of the other logic chips through the conductive structure of the substrate for transfer of signals between the logic chips. The logic chips can be adapted to simultaneously execute a set of instructions of a given thread of a process. The contacts of the memory chip can be directly electrically connected to the signal contacts of at least one of the logic chips through the conductive structure of the substrate. | 10-25-2012 |
20120267789 | VIAS IN POROUS SUBSTRATES - A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction. | 10-25-2012 |
20120267798 | MULTIPLE DIE FACE-DOWN STACKING FOR TWO OR MORE DIE - A microelectronic assembly is disclosed that comprises a substrate having first and second openings, a first microelectronic element and a second microelectronic element in a face-down position. The first element has an active surface facing the front surface of the substrate and bond pads aligned with the first opening, a rear surface remote therefrom, and an edge extending between the front and rear surfaces. The second microelectronic element has a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, and bond pads at the front surface of the second microelectronic element aligned with the second opening. | 10-25-2012 |
20120273933 | THREE-DIMENSIONAL SYSTEM-IN-A-PACKAGE - A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having a minimum thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements. | 11-01-2012 |
20120286416 | SEMICONDUCTOR CHIP PACKAGE ASSEMBLY AND METHOD FOR MAKING SAME - A microelectronic assembly may include a microelectronic element having a plurality of element contacts at a face thereof, and a compliant dielectric element having a Young's modulus of less than about two gigapascal (GPa) and substrate contacts at a first surface joined to the element contacts. The substrate contacts may be electrically connected with terminals at a second surface of the compliant dielectric element that opposes the first surface, through conductive vias in the compliant dielectric element. A rigid underfill may be between the face of the microelectronic element and the first surface of the compliant dielectric element. The terminals may be usable for bonding the microelectronic assembly to corresponding contacts of a component external to the microelectronic assembly. | 11-15-2012 |
20120313238 | SEMICONDUCTOR CHIP PACKAGE ASSEMBLY AND METHOD FOR MAKING SAME - A microelectronic assembly may include a substrate containing a dielectric element having first and second opposed surfaces. The dielectric element may include a first dielectric layer adjacent the first surface, and a second dielectric layer disposed between the first dielectric layer and the second surface. A Young's modulus of the first dielectric layer may be at least 50% greater than the Young's modulus of the second dielectric layer, which is less than two gigapascal (GPa). A conductive structure may extend through the first and second dielectric layers and electrically connect substrate contacts at the first surface with terminals at the second surface. The substrate contacts may be joined with contacts of a microelectronic element through conductive masses, and a rigid underfill may be between the microelectronic element and the first surface. The terminals may be usable to bond the microelectronic assembly to contacts of a component external to the microelectronic assembly. | 12-13-2012 |
20120313253 | FAN-OUT WLP WITH PACKAGE - A microelectronic package includes a microelectronic unit and a substrate. The microelectronic unit includes a microelectronic element having contacts on a front face. A dielectric material has a first surface substantially flush with the front face of the microelectronic element. Conductive traces have at least portions extending along the front face away from the contacts, at least some of which also extend along the first surface of the dielectric material. Contacts are connected with the traces, at least some of which are disposed at the first surface of the dielectric material. The substrate has first and second opposed surfaces and an edge extending therebetween, the first surface facing the front face of the microelectronic unit, and the second surface having a plurality of terminals thereon configured for electrical connection with at least one external component. Masses of conductive matrix material join the terminals with the redistribution contacts. | 12-13-2012 |
20120313264 | CHIP WITH SINTERED CONNECTIONS TO PACKAGE - A microelectronic package and method of making same are provided. The package includes a substrate having first and second opposed surfaces, an edge surface extending therebetween, a plurality of terminals, and a plurality of conductive elements electrically connected with the terminals. The edge surface can be disposed at a periphery of the substrate or can be the edge surface of an aperture within the substrate. A microelectronic element has a front face and contacts thereon, with at least some of the contacts being adjacent to the edge surface of the substrate. A dielectric material overlies the edge surface of the substrate and defines a sloping surface between the front face of the microelectronic element and the substrate. A conductive matrix material defines a plurality of conductive interconnects extending along the sloping surface. The conductive interconnects electrically interconnect respective ones of the contacts with the conductive elements. | 12-13-2012 |
20120314384 | LOW-STRESS TSV DESIGN USING CONDUCTIVE PARTICLES - A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via. | 12-13-2012 |
20120326313 | SINGLE EXPOSURE IN MULTI-DAMASCENE PROCESS - Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed. | 12-27-2012 |
20120326326 | Systems and Methods for Producing Flat Surfaces in Interconnect Structures - Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure. | 12-27-2012 |
20130010441 | MICROELECTRONIC ELEMENTS WITH POST-ASSEMBLY PLANARIZATION - A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure. | 01-10-2013 |
20130014978 | Electrical Barrier LayersAANM Uzoh; CyprianAACI San JoseAAST CAAACO USAAGP Uzoh; Cyprian San Jose CA USAANM Oganesian; VageAACI Palo AltoAAST CAAACO USAAGP Oganesian; Vage Palo Alto CA USAANM Mohammed; IlyasAACI Santa ClaraAAST CAAACO USAAGP Mohammed; Ilyas Santa Clara CA USAANM Haba; BelgacemAACI SaratogaAAST CAAACO USAAGP Haba; Belgacem Saratoga CA USAANM Savalia; PiyushAACI Santa ClaraAAST CAAACO USAAGP Savalia; Piyush Santa Clara CA USAANM Mitchell; CraigAACI San JoseAAST CAAACO USAAGP Mitchell; Craig San Jose CA US - Barrier layers for use in electrical applications. In some embodiments the barrier layer is a laminated barrier layer. In some embodiments the barrier layer includes a graded barrier layer. | 01-17-2013 |
20130026645 | LOW STRESS VIAS - A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region. | 01-31-2013 |
20130032944 | MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC ELEMENTS AND METHOD FOR MANUFACTURE THEREOF - A microelectronic package may include a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing a top surface of the package. The front face of the first element may be adjacent the top surface, and the first element may overlie the front face of the second element such that at least a portion of the front face of the second element having an element contact thereon extends beyond an edge of the first element. A conductive structure may electrically connect a first terminal at the top surface to an element contact at the front face of the second element, and include a continuous monolithic metal feature extending along the top surface and through at least a portion of an encapsulant, which is between the top surface and the front face of the second element, towards the element contact. | 02-07-2013 |
20130068516 | HIGH IO SUBSTRATES AND INTERPOSERS WITHOUT VIAS - An interconnection component includes a substrate having first and second opposed major surfaces defining a thickness of less than 1000 microns and a first slot extending between the first and second surfaces, the first slot being enclosed by the substrate at the first and second surfaces. The first slot defines an edge surface between the first surface and the second surface. First conductive traces extend along the first surface and are electrically connected with first contact pads that overlie the first surface. Second conductive traces extend along the second surface and electrically connected with second contact pads that overlie the second surface. Interconnect traces extend along the edge surface of the first slot. Each interconnect trace directly connects at least one first trace with at least one second trace. | 03-21-2013 |
20130099387 | MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOF - A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metallized vias and traces formed in contact with the second chip contacts. | 04-25-2013 |
20130119520 | CHIPS WITH HIGH FRACTURE TOUGHNESS THROUGH A METAL RING - A microelectronic element is disclosed that includes a semiconductor chip and a continuous monolithic metallic edge-reinforcement ring that covers each of the plurality of edge surfaces of the semiconductor chip and extending onto the front surface. The semiconductor chip may have front and rear opposed surfaces and a plurality of contacts at the front surface and edge surfaces extending between the front and rear surfaces. The semiconductor chip may also embody at least an active device or a passive device. | 05-16-2013 |
20130122747 | CAVITIES CONTAINING MULTI-WIRING STRUCTURES AND DEVICES - An interconnection component includes an element with an opening, a plurality of conductors electrically insulted from one another extending through the opening, and a plurality of second contacts electrically insulated from one another. The element is comprised of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. At least some of the conductors extend along at least one inner surface of the opening. The conductors define a plurality of wettable first contacts at the first surface. The first contacts are at least partially aligned with the opening in a direction of the thickness and electrically insulated from one another. | 05-16-2013 |
20130126867 | HIGH YIELD SUBSTRATE ASSEMBLY - High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates. | 05-23-2013 |
20130127062 | MULTIPLE DIE FACE-DOWN STACKING FOR TWO OR MORE DIE - A microelectronic assembly can include a substrate having first and second surfaces each extending in first and second transverse directions, a peripheral edge extending in the second direction, first and second openings extending between the first and second surfaces, and a peripheral region of the second surface extending between the peripheral edge and one of the openings. The assembly can also include a first microelectronic element having a front surface facing the first surface, a rear surface opposite therefrom, and an edge extending between the front and rear surfaces. The assembly can also include a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond the edge of the first microelectronic element. The assembly can also include a plurality of terminals exposed at the second surface, at least one of the terminals being disposed at least partially within the peripheral region. | 05-23-2013 |
20130134602 | FLIP CHIP PACKAGE FOR DRAM WITH TWO UNDERFILL MATERIALS - A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill. | 05-30-2013 |
20130203216 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE - A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby. | 08-08-2013 |
20130214296 | HEAT SPREADING SUBSTRATE WITH EMBEDDED INTERCONNECTS - Heat spreading substrate with embedded interconnects. In an embodiment in accordance with the present invention, an apparatus includes a metal parallelepiped comprising a plurality of wires inside the metal parallelepiped. The plurality of wires have a different grain structure than the metal parallelepiped. The plurality of wires are electrically isolated from the metal parallelepiped. The plurality of wires may be electrically isolated from one another. | 08-22-2013 |
20130215121 | HEAT SPREADING SUBSTRATE - Heat spreading substrate. In accordance with an embodiment of the present invention, an apparatus includes a thermally conductive, electrically insulating regular solid, a first electrically conductive coating mechanically coupled to a first edge of the regular solid and a second electrically conductive coating mechanically coupled to a second edge of the regular solid. The first and the second electrically conductive coatings are electrically isolated from one another and the faces of the first electrically conductive coating, the second electrically conductive coating and the regular solid are substantially co-planar. The primary and secondary surfaces of the regular solid may be free of electrically conductive materials. | 08-22-2013 |
20130249116 | MICROELECTRONIC PACKAGE - A microelectronic package includes a lower unit having a lower unit substrate with conductive features and a top and bottom surface. The lower unit includes one or more lower unit chips overly/ing the top surface of the lower unit substrate that are electrically connected to the conductive features of the lower unit substrate. The microelectronic package also includes an upper unit including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips overlying the top surface of the upper unit substrate and electrically connected to the conductive features of the upper unit substrate by connections extending within the hole. The upper unit may include an upper unit encapsulant that covers the connections of the upper unit and the one or more upper unit chips. | 09-26-2013 |
20130273693 | OFF-CHIP VIAS IN STACKED CHIPS - A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements. | 10-17-2013 |
20130288412 | HIGH YIELD SUBSTRATE ASSEMBLY - High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates. | 10-31-2013 |
20130300000 | MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC ELEMENTS AND METHOD FOR MANUFACTURE THEREOF - A microelectronic package may include a stacked microelectronic unit including at least first and second vertically stacked microelectronic elements each having a front face facing a top surface of the package. The front face of the first element may be adjacent the top surface, and the first element may overlie the front face of the second element such that at least a portion of the front face of the second element having an element contact thereon extends beyond an edge of the first element. A conductive structure may electrically connect a first terminal at the top surface to an element contact at the front face of the second element, and include a continuous monolithic metal feature extending along the top surface and through at least a portion of an encapsulant, which is between the top surface and the front face of the second element, towards the element contact. | 11-14-2013 |
20130313680 | HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS - A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates. | 11-28-2013 |
20130313716 | SUBSTRATE-LESS STACKABLE PACKAGE WITH WIRE-BOND INTERCONNECT - A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer. | 11-28-2013 |
20130334698 | MICROELECTRONIC ASSEMBLY TOLERANT TO MISPLACEMENT OF MICROELECTRONIC ELEMENTS THEREIN - A microelectronic assembly tolerant to misplacement of microelectronic elements therein may include a molded structure containing a plurality of microelectronic elements. Each microelectronic element has elements contacts having first and second dimensions in respective first and second directions that are transverse to each other, where the first dimension is at least twice the second dimension. In addition, the assembly may include a conductive redistribution layer including conductive vias extending through a dielectric layer to the element contacts of the respective microelectronic elements, where the conductive vias have a third dimension in a third direction and a fourth dimension in a fourth direction, and where the fourth direction is transverse to the third and first directions and the fourth dimension is greater than the third dimension. | 12-19-2013 |
20130341804 | SIMULTANEOUS WAFER BONDING AND INTERCONNECT JOINING - Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip. | 12-26-2013 |
20140008669 | PARALLEL PLATE SLOT EMISSION ARRAY - Parallel plate slot emission array. In accordance with an embodiment of the present invention, an article of manufacture includes a side-emitting light emitting diode configured to emit light from more than two surfaces. The article of manufacture includes a first sheet electrically and thermally coupled to a first side of the light emitting diode, and a second sheet electrically and thermally coupled to a second side of the light emitting diode. The article of manufacture further includes a plurality of reflective surfaces configured to reflect light from all of the surfaces of the light emitting diode through holes in the first sheet. The light may be reflected via total internal reflection. | 01-09-2014 |
20140008676 | OPTICAL ENHANCEMENT OF LIGHT EMITTING DEVICES - Optical enhancement of light emitting devices. In accordance with an embodiment of the present invention, an apparatus includes an optical enhancement layer comprising nanoparticles. Each of the nanoparticles includes an electrically conductive core surrounded by an electrically insulating shell. The optical enhancement layer is disposed on a top semiconductor layer in a preferred path of optical emission of a light emitting device. The nanoparticles may enhance the light emission of the light emitting device due to emitter-surface plasmon coupling. | 01-09-2014 |
20140014894 | HIGH PERFORMANCE LIGHT EMITTING DIODE WITH VIAS - High performance light emitting diode with vias. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a plurality of filled vias configured to connect a doped region on one side of the light emitting diode to a plurality of contacts on the other side of the light emitting diode. The filled vias may comprise less that 10% of a surface area of the light emitting diode. | 01-16-2014 |
20140021641 | MICROELECTRONIC PACKAGES HAVING CAVITIES FOR RECEIVING MICROELECTRONIC ELEMENTS - Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts. | 01-23-2014 |
20140035153 | RECONSTITUTED WAFER-LEVEL PACKAGE DRAM - A microelectronic package includes first and second encapsulated microelectronic elements, each of which includes a semiconductor die having a front face and contacts thereon. An encapsulant contacts at least an edge surface of each semiconductor die and extends in at least one lateral direction therefrom. Electrically conductive elements extend from the contacts and over the front face to locations overlying the encapsulant. The first and second microelectronic elements are affixed to one another such that one of the front or back surfaces of one of the first and second semiconductor dies is oriented towards one of the front or back surfaces of the other of the first and second semiconductor dies. A plurality of electrically conductive interconnects extend through the encapsulants of the first and second microelectronic elements and are electrically connected with at least one semiconductor die of the first and second microelectronic elements by the conductive elements. | 02-06-2014 |
20140036454 | BVA INTERPOSER - A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds. | 02-06-2014 |
20140045285 | PARALLEL PLATE SLOT EMISSION ARRAY - In accordance with an embodiment of the present invention, an article of manufacture includes a side-emitting light emitting diode configured to emit light from more than two surfaces. The article of manufacture includes a first sheet electrically and thermally coupled to a first side of the light emitting diode, and a second sheet electrically and thermally coupled to a second side of the light emitting diode. The article of manufacture further includes a plurality of reflective surfaces configured to reflect light from all of the surfaces of the light emitting diode through holes in the first sheet. The light may be reflected via total internal reflection. | 02-13-2014 |
20140048954 | STACKED MICROELECTRONIC ASSEMBLY WITH TSVS FORMED IN STAGES WITH PLURAL ACTIVE CHIPS - A microelectronic assembly is provided in which first and second electrically conductive pads exposed at front surfaces of first and second microelectronic elements, respectively, are juxtaposed, each of the microelectronic elements embodying active semiconductor devices. An electrically conductive element may extend within a first opening extending from a rear surface of the first microelectronic element towards the front surface thereof, within a second opening extending from the first opening towards the front surface of the first microelectronic element, and within a third opening extending through at least one of the first and second pads to contact the first and second pads. Interior surfaces of the first and second openings may extend in first and second directions relative to the front surface of the first microelectronic element, respectively, to define a substantial angle. | 02-20-2014 |
20140057370 | DUAL WAFER SPIN COATING - A method of bonding a first substrate and a second substrate includes the steps of rotating first substrate with an adhesive mass thereon, and second substrate contacting the mass and overlying the first substrate, controlling a vertical height of a heated control platen spaced apart from and not contacting the second substrate so as to control a temperature of the adhesive mass, so as to at least one of bond the first and second substrates in alignment with one another, or achieve a sufficiently planar adhesive interface between the first and second substrates. | 02-27-2014 |
20140097546 | MULTI-FUNCTION AND SHIELDED 3D INTERCONNECTS - A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element. | 04-10-2014 |
20140099754 | COMPLIANT INTERCONNECTS IN WAFERS - A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit. | 04-10-2014 |
20140131851 | STRUCTURE FOR MICROELECTRONIC PACKAGING WITH TERMINALS ON DIELECTRIC MASS - A structure may include a spacer element overlying a first portion of a first surface of a substrate; first terminals at a second surface of the substrate opposite the first surface; and second terminals overlying a third surface of the spacer element facing away from the first surface. Traces extend from the second terminals along an edge surface of the spacer element that extends from the third surface towards the first surface, and may be electrically coupled between the second terminals and the first terminals or electrically conductive elements at the first surface. The spacer element may at least partially define a second portion of the first surface, which is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some of the conductive elements are at the second portion and may permit connection with such microelectronic element. | 05-15-2014 |
20140131892 | CHIP ASSEMBLY HAVING VIA INTERCONNECTS JOINED BY PLATING - An assembly and method of making same are provided. The assembly can be formed by juxtaposing a first electrically conductive element overlying a major surface of a first semiconductor element with an electrically conductive pad exposed at a front surface of a second semiconductor element. An opening can be formed extending through the conductive pad of the second semiconductor element and exposing a surface of the first conductive element. The opening may alternatively be formed extending through the first conductive element. A second electrically conductive element can be formed extending at least within the opening and electrically contacting the conductive pad and the first conductive element. A third semiconductor element can be positioned in a similar manner with respect to the second semiconductor element. | 05-15-2014 |
20140141568 | FLIP CHIP PACKAGE FOR DRAM WITH TWO UNDERFILL MATERIALS - A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill. | 05-22-2014 |
20140141597 | CHIPS WITH HIGH FRACTURE TOUGHNESS THROUGH A METAL RING - A method of making an edge-reinforced microelectronic element is disclosed. The steps include mechanically cutting along dicing lanes of a substrate at least partially through a thickness thereof to form a plurality of edge surfaces extending away from a front surface thereof and forming a continuous monolithic metallic edge-reinforcement ring that covers each of the plurality of edge surfaces and extends onto the front surface. The front surface may have a plurality of contacts thereat and the substrate may embody a plurality of microelectronic elements. | 05-22-2014 |
20140159248 | HIGH PERFORMANCE PACKAGE ON PACKAGE - A microelectronic assembly can include a first package comprising a processor and a second package electrically connected to the first package. The second package can include two or more microelectronic elements each having memory storage array function and contacts at a respective element face, upper and lower opposite package faces, upper and lower terminals at the respective upper and lower package faces, and electrically conductive structure extending through the second package. At least portions of edges of respective microelectronic elements of the two or more microelectronic elements can be spaced apart from one another, so as to define a central region between the edges that does not overlie any of the element faces of the microelectronic elements of the second package. The electrically conductive structure can be aligned with the central region and can electrically connect the lower terminals with at least one of: the upper terminals or the contacts. | 06-12-2014 |
20140175440 | NON-CRYSTALLINE INORGANIC LIGHT EMITTING DIODE - Non-crystalline inorganic light emitting diode. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a non-crystalline inorganic light emission layer and first and second semiconducting non-crystalline inorganic charge transport layers surrounding the light emission layer. The light emission layer may be amorphous. The charge transport layers may be configured to inject one type of charge carrier and block the other type of charge carrier. | 06-26-2014 |
20140175671 | STRUCTURE FOR MICROELECTRONIC PACKAGING WITH BOND ELEMENTS TO ENCAPSULATION SURFACE - A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element. | 06-26-2014 |
20140179061 | THIN WAFER HANDLING - A first area of a first surface of an encapsulated component can be thinned, the component including: a semiconductor chip having an active surface opposite the first surface, and an encapsulant extending outwardly from edges of the semiconductor chip. An entire area of the active surface may be aligned with the first area. After the abrading, a second area of the encapsulated component beyond the first area may have a thickness greater than a thickness of the first area. The second area can be configured to fully support the abraded encapsulated component in a state of the encapsulated component being manipulated by handling equipment. | 06-26-2014 |
20140201994 | LOW-STRESS TSV DESIGN USING CONDUCTIVE PARTICLES - A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via. | 07-24-2014 |
20140203452 | ACTIVE CHIP ON CARRIER OR LAMINATED CHIP HAVING MICROELECTRONIC ELEMENT EMBEDDED THEREIN - A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect the additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity. | 07-24-2014 |
20140206147 | STACKED MICROELECTRONIC ASSEMBLY WITH TSVS FORMED IN STAGES AND CARRIER ABOVE CHIP - A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element. A conductive element extends within the first and second openings and contacts the at least one conductive pad. | 07-24-2014 |
20140206184 | INTERPOSER HAVING MOLDED LOW CTE DIELECTRIC - A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel. | 07-24-2014 |
20140210104 | NON-LITHOGRAPHIC FORMATION OF THREE-DIMENSIONAL CONDUCTIVE ELEMENTS - A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate. | 07-31-2014 |
20140212996 | MICROELECTRONIC PACKAGE WITH STACKED MICROELECTRONIC UNITS AND METHOD FOR MANUFACTURE THEREOF - A microelectronic package may include a first microelectronic unit including a semiconductor chip having first chip contacts, an encapsulant contacting an edge of the semiconductor chip, and first unit contacts exposed at a surface of the encapsulant and electrically connected with the first chip contacts. The package may include a second microelectronic unit including a semiconductor chip having second chip contacts at a surface thereof, and an encapsulant contacting an edge of the chip of the second unit and having a surface extending away from the edge. The surfaces of the chip and the encapsulant of the second unit define a face of the second unit. Package terminals at the face may be electrically connected with the first unit contacts through bond wires electrically connected with the first unit contacts, and the second chip contacts through metalized vias and traces formed in contact with the second chip contacts. | 07-31-2014 |
20140213021 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A method of making a microelectronic assembly can include molding a dielectric material around at least two conductive elements which project above a height of a substrate having a microelectronic element mounted thereon, so that remote surfaces of the conductive elements remain accessible and exposed within openings extending from an exterior surface of the molded dielectric material. The remote surfaces can be disposed at heights from said surface of said substrate which are lower or higher than a height of the exterior surface of the molded dielectric material from the substrate surface. The conductive elements can be arranged to simultaneously carry first and second different electric potentials: e.g., power, ground or signal potentials. | 07-31-2014 |
20140217584 | FLOW UNDERFILL FOR MICROELECTRONIC PACKAGES - A microelectronic assembly includes a first component with first conductive elements; a second component with second conductive elements; a bond metal; and an underfill layer. The posts have a height above the respective surface from which the posts project. A bond metal can be disposed between respective pairs of conductive elements, each pair including at least one of the posts and at least one of the first or second conductive elements confronting the at least one post. The bond metal can contact edges of the posts along at least one half the height of the posts. An underfill layer contacts and bonds the first and second surfaces of the first and second components. A residue of the underfill layer may be present at at least one interfacial surfaces between at least some of the posts and the bond metal or may be present within the bond metal. | 08-07-2014 |
20140239514 | MICROELECTRONIC PACKAGE WITH CONSOLIDATED CHIP STRUCTURES - A chip package has multiple chips that may be arranged side-by-side or in a staggered, stair step arrangement. The contacts of the chips are connected to interconnect pads carried on the chips themselves or on a redistribution substrate. The interconnect pads desirably are arranged in a relatively narrow interconnect zone, such that the interconnect pads can be readily wire-bonded or otherwise connected to a package substrate. | 08-28-2014 |
20140262457 | POROUS ALUMINA TEMPLATES FOR ELECTRONIC PACKAGES - Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing surfaces and a plurality of pores, each pore extending in a first direction from the first surface towards the second surface, wherein alumina extends along a wall of each pore; a plurality of electrically conductive connection elements extending in the first direction, consisting essentially of aluminum and being electrically isolated from one another by at least the alumina; a first conductive path provided at the first surface for connection with a first component external to the interposer; and a second conductive path provided at the second surface for connection with a second component external to the interposer, wherein the first and second conductive paths are electrically connected through at least some of the connection elements. | 09-18-2014 |
20140273393 | HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS - A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape. | 09-18-2014 |
20140308987 | WEARABLE ULTRA-THIN MINIATURIZED MOBILE COMMUNICATIONS - A device is provided with a housing adapted to engage a portion of a head of a user, such as the ear of the user. The device includes a camera component adapted to face in the same direction as the user when engaged with the portion of the head of the user. The device may be adapted to be controlled using voice commands from the user | 10-16-2014 |
20140332981 | LOW-STRESS VIAS - A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region. | 11-13-2014 |
20140342503 | COMPLIANT INTERCONNECTS IN WAFERS - A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit. | 11-20-2014 |
20140357021 | MULTI-CHIP MODULE WITH STACKED FACE-DOWN CONNECTED DIES - A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component. Signal contacts of each logic chip can be directly electrically connected to signal contacts of the other logic chips through the conductive structure of the substrate for transfer of signals between the logic chips. The logic chips can be adapted to simultaneously execute a set of instructions of a given thread of a process. The contacts of the memory chip can be directly electrically connected to the signal contacts of at least one of the logic chips through the conductive structure of the substrate. | 12-04-2014 |
20140367866 | MEMORY MODULE IN A PACKAGE - A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals. | 12-18-2014 |
20150014847 | MICROELECTRONIC ASSEMBLIES WITH STACK TERMINALS COUPLED BY CONNECTORS EXTENDING THROUGH ENCAPSULATION - A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. An encapsulation separates respective pairs of coupled first and second connectors from one another and may encapsulate the microelectronic element and fill spaces between the support elements. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns. | 01-15-2015 |
20150014850 | INTERCONNECT STRUCTURE - A microelectronic assembly includes first and second surfaces, a first thin conductive element, a first conductive projection, and a first fusible mass. The first thin conductive element includes a face that has first and second regions. The first conductive projection covers the first region of the first face. A barrier may be formed along a portion of the first region. The second face includes a second conductive projection that extends away therefrom. The first fusible metal mass connects the first conductive projection to the second conductive projection such that the first surface of the first face is oriented toward the second surface of the second substrate. The first mass extends along a portion of the first conductive projection to a location toward the first edge of the barrier. The barrier is disposed between the first thin element and the first metal mass. | 01-15-2015 |
20150014856 | MICROELECTRONIC ASSEMBLIES HAVING REINFORCING COLLARS ON CONNECTORS EXTENDING THROUGH ENCAPSULATION - A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. Dielectric reinforcing collars are provided on outer surfaces of the first connectors, second connectors or both, and an encapsulation separates pairs of coupled connectors from one another and may fill spaces between support elements. | 01-15-2015 |
20150021788 | Multi-Function and Shielded 3D Interconnects - A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element. | 01-22-2015 |
20150034371 | STRUCTURE FOR MICROELECTRONIC PACKAGING WITH BOND ELEMENTS TO ENCAPSULATION SURFACE - A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element. | 02-05-2015 |
20150041208 | MICRO MECHANICAL ANCHOR FOR 3D ARCHITECTURE - Components and methods of making the same are disclosed herein. In one embodiment, a method of forming a component comprises forming metal anchoring elements at a first surface of a support element having first and second oppositely facing surfaces, the support element having a thickness extending in a first direction between the first and second surfaces, wherein each anchoring element has a downwardly facing overhang surface; and then forming posts having first ends proximate the first surface and second ends disposed above the respective first ends and above the first surface, wherein a laterally extending portion of each post contacts at least a first area of the overhang surface of the respective anchoring element and extends downwardly therefrom, and the overhang surface of the anchoring element resists axial and shear forces applied to the posts at positions above the anchoring elements. | 02-12-2015 |
20150043190 | EMBEDDED PACKAGING WITH PREFORMED VIAS - Microelectronic assemblies and methods of making the same are disclosed. In some embodiments, a microelectronic assembly includes a microelectronic element having edge surfaces bounding a front surface and contacts at the front surface; rigid metal posts disposed between at least one edge surface and a corresponding edge of the assembly, each metal post having a sidewall separating first and second end surfaces, the sidewalls have a root mean square (rms) surface roughness of less than about 1 micron; a encapsulation contacting at least the edge surfaces and the sidewalls; an insulation layer overlying the encapsulation; connection elements extending through the insulation layer, wherein at least some connection elements have cross sections smaller than those of the metal posts; a redistribution structure deposited on the insulation layer and electrically connecting first terminals with corresponding metal posts through the first connection elements, some metal posts electrically coupled with contacts of microelectronic element. | 02-12-2015 |
20150044823 | MICROELECTRONIC PACKAGE WITH INTEGRATED BEARING SURFACES - A method of forming a wire bond having a free end includes joining an end of a metal wire to a conductive element at a surface of a first component, the end of the metal wire being proximate a surface of a bonding tool adjacent an aperture through which the metal wire extends. A predetermined length of the metal wire is drawn out from the aperture. The surface of the bonding tool is used to plastically deform a region of the metal wire between the surface of the bonding tool and a metal element at the surface of the first component. The bonding tool then applies tension to the metal wire to cause a first portion of the metal wire having the end joined to the conductive element to detach from a remaining portion of the metal wire at the plastically deformed region. | 02-12-2015 |
20150044824 | Fan-Out WLP With Package - The present disclosure is directed to a method for making a microelectronic package that includes assembling a microelectronic unit with a substrate, and electrically connecting redistribution contacts on the microelectronic unit and terminals on the substrate with a conductive matrix material extending within at least one opening extending through the substrate. | 02-12-2015 |
20150048524 | STACKED MICROELECTRONIC PACKAGES HAVING AT LEAST TWO STACKED MICROELECTRONIC ELEMENTS ADJACENT ONE ANOTHER - A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element. | 02-19-2015 |
20150069639 | Substrate-Less Stackable Package With Wire-Bond Interconnect - A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer. | 03-12-2015 |
20150079733 | THREE-DIMENSIONAL SYSTEM-IN-A-PACKAGE - A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having at least a portion having a thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements. | 03-19-2015 |