Patent application number | Description | Published |
20100042811 | METHOD FOR MANAGING BRANCH INSTRUCTIONS AND A DEVICE HAVING BRANCH INSTRUCTION MANAGEMENT CAPABILITIES - A method for managing branch instructions, the method includes: providing, to pipeline stages of a processor, multiple variable length groups of instructions; wherein each pipeline stage executes a group of instruction during a single execution cycle; receiving, at a certain execution cycle, multiple instruction fetch requests from multiple pipeline stages, each pipeline stage that generates an instruction fetch request stores a variable length group of instructions that comprises a branch instruction; sending to the fetch unit an instruction fetch command that is responsive to a first in order branch instruction in the pipeline stages; wherein if the first in order fetch command is a conditional fetch command then the instruction fetch command comprises a resolved target address; wherein the sending of the instruction fetch command is restricted to a single instruction fetch command per a single execution cycle. | 02-18-2010 |
20100049954 | METHOD FOR SPECULATIVE EXECUTION OF INSTRUCTIONS AND A DEVICE HAVING SPECULATIVE EXECUTION CAPABILITIES - A method for speculative execution of instructions, the method includes: decoding a compare instruction; speculatively executing, in a continuous manner, conditional instructions that are conditioned by a condition that is related to a resolution of the compare instruction and are decoded during a speculation window that starts at the decoding of the compare instruction and ends when the compare instruction is resolved; and stalling an execution of a non-conditional instruction that is dependent upon an outcome of at least one of the conditional instructions, until the speculation window ends. | 02-25-2010 |
20100049958 | METHOD FOR EXECUTING AN INSTRUCTION LOOPS AND A DEVICE HAVING INSTRUCTION LOOP EXECUTION CAPABILITIES - A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions; (ii) requesting from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop; and (iii) selecting, during iterations of the instruction loop, whether to provide to a dispatch unit one of the first instructions of the instruction loop or another instruction that is fetched by the fetch unit; wherein the first instructions of the instruction loop are stored at the dispatch unit. | 02-25-2010 |
20130290686 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR CALCULATING A PREDICATE VALUE - An integrated circuit device comprises at least one instruction processing module arranged to perform branch predication. The at least one instruction processing module comprises at least one predicate calculation module arranged to receive as an input at least one result vector for a predicate function and at least one conditional parameter value therefor and output a predicate result value from the at least one result vector based at least partly on the at least one received conditional parameter value. | 10-31-2013 |
20130297578 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR DETERMINING AN INDEX OF AN EXTREME VALUE WITHIN AN ARRAY OF VALUES - An integrated circuit device comprises at least one digital signal processor, DSP, module, the at least one DSP module comprising a plurality of data registers and at least one data execution unit, DEU, module arranged to execute operations on data stored within the data registers. The at least one DEU module is arranged to, in response to receiving an extreme value index instruction, compare a previous extreme value located within a first data register set of the DSP module with at least one input vector data value located within a second data register set of the DSP module, and determine an extreme value thereof. The at least one DEU module is further arranged to, if the determined extreme value comprises an input vector data value located within the second data register set, store the determined extreme value in the first data register set, determine an index value for the determined extreme value, and store the determined index value in the first data register set. | 11-07-2013 |
20130326200 | INTEGRATED CIRCUIT DEVICES AND METHODS FOR SCHEDULING AND EXECUTING A RESTRICTED LOAD OPERATION - An integrated circuit device comprising at least one instruction processing module arranged to compare validation data with data stored within a target register upon receipt of a load validation instruction. Wherein, the instruction processing module is further arranged to proceed with execution of a next sequential instruction if the validation data matches the stored data within the target register, and to load the validation data into the target register if the validation data does not match the stored data within the target register. | 12-05-2013 |
20140013087 | PROCESSOR SYSTEM WITH PREDICATE REGISTER, COMPUTER SYSTEM, METHOD FOR MANAGING PREDICATES AND COMPUTER PROGRAM PRODUCT - A processor system is adapted to carry out a predicate swap instruction of an instruction set to swap, via a data pathway, predicate data in a first predicate data location of a predicate register with data in a corresponding additional predicate data location of a first additional predicate data container and to swap, via a data pathway, predicate data in a second predicate storage location of the predicate register with data in a corresponding additional predicate data location in a second additional predicate data container. | 01-09-2014 |
20140013088 | INTEGRATED CIRCUIT DEVICE AND METHODS OF PERFORMING BIT MANIPULATION THEREFOR - An integrated circuit device comprising at least one instruction processing module arranged to receive a bit-manipulation instruction, and in response to receiving the bit-manipulation instruction to select at least one bit from at least one source data register in accordance with a value of at least one control bit, select from candidate values a manipulation value for the at least one selected bit in accordance with a value of at least one further control bit, and store the selected manipulation value for the at least one selected bit in at least one output data register. | 01-09-2014 |
20140019990 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR ENABLING CROSS-CONTEXT ACCESS - An integrated circuit device comprising an instruction processing module for performing operations on data in accordance with received instructions. The instruction processing module comprises a context selector unit arranged to selectively provide access to at least one process attribute(s) within a plurality of process contexts in accordance with at least one context selector value received thereby. The instruction processing module is arranged to receive an instruction comprising a context indication for a process attribute with which an operation is to be performed, provide the context selector value based at least partly on the context indication to the context selector unit, and execute the operation to be performed with the process attribute for at least one process context to which the context selector unit provides access in accordance with the context selector value. | 01-16-2014 |
20150082005 | PROCESSING SYSTEM AND METHOD OF INSTRUCTION SET ENCODING SPACE UTILIZATION - A processing system comprises a processing device; a first instruction set encoded in a first encoding space and comprising one or more first instructions; a second instruction set encoded in a second encoding space different from the first encoding space and comprising two or more orthogonal second instructions; and an instruction encoder arranged to encode and encapsulate subsets of the second instructions in instruction containers, each instruction container sized to comprise a plurality of the second instructions. | 03-19-2015 |