Patent application number | Description | Published |
20120210855 | SYSTEM AND METHOD FOR LAUNCHING COUNTERMEASURES TO MISSILE ATTACK - A system and method for launching countermeasures, such as flares and chaff, from an aircraft under attack by a missile. A plurality of countermeasure launchers are mounted preferably on the two sides and tail and nose of the aircraft and communicate with a missile detection and warning system mounted in the aircraft. Based upon the circumstances reported by the warning system, the appropriate countermeasure weapon or weapons are selected and dispensed. The circumstances reported are based upon the angle of elevation and azimuth angle of the approaching missile in relation to the aircraft and distance of the missile from the aircraft. Also, the speed and altitude of the aircraft are utilized in determining the countermeasures applied. The various responses are distinguished by the number and types of countermeasures dispensed, the dispense time of the countermeasures and the particular launcher or launchers used, based upon the type of aircraft being protected. | 08-23-2012 |
20140222397 | FRONT-END SIGNAL GENERATOR FOR HARDWARE IN-THE-LOOP SIMULATION - A front-end signal generator for hardware-in-the-loop simulators of a simulated missile is disclosed. The front-end signal generator is driven by the Digital Scene And Reticle Simulation-Hardware In The Loop (DSARS-HITL) simulator. The simulator utilizes a computer to calculate irradiance on an Electro-Optical/Infrared (EO/IR) detector. The generator converts irradiance values into voltages that are injected into the missile's electronics during simulation. The conversion is done with low latency and a high dynamic range sufficient for hardware-in-the-loop simulation. The generator is capable of emulating laser pulse inputs that would be present during laser-based jammer countermeasures. Computer control of the generator occurs via front-panel-data-port (FPDP). | 08-07-2014 |
20150177365 | FOURIER TRANSFORM-BASED JAMMING TECHNIQUES - Techniques are disclosed for producing and/or optimizing jamming codes for use in directional infrared countermeasures (DIRCM) systems. In some embodiments, Fourier analysis may be implemented to produce jamming codes which more efficiently (e.g., time efficient, power efficient) and/or more reliably (e.g., no frequency gaps) achieve optical break-lock (OBL) of infrared (IR)-seeking missiles/threats over a broad range of frequencies (e.g., short-wavelength IR, mid-wavelength IR), as compared to heritage jamming code methodologies. Some embodiments may be implemented in military/defense applications (e.g., protection of military/tactical aircraft or other vehicles); some other embodiments may be implemented in non-military/commercial applications (e.g., protection of domestic, civilian, and/or commercial aircraft or other vehicles). Some embodiments may be implemented to protect against IR-seeking air-to-air missiles (AAMs), surface-to-air missiles (SAMs), and/or man-portable air-defense systems (MANPADS/MPADS). Numerous configurations and variations will be apparent in light of this disclosure. | 06-25-2015 |
Patent application number | Description | Published |
20080247255 | ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY ARRAY AND METHODS OF USING THE SAME - An electronic device can include a first memory cell and a second memory cell. The first memory cell can include a first source, and a second memory cell can include a second source. The first memory cell and the second memory cell can lie within a same sector of a memory array. In one embodiment, erasing the electronic device can include erasing the first memory cell while inhibiting the erase of the second memory cell. A third memory cell can have a third source and lie within another sector. In another embodiment, inhibiting the erase of the first memory cell can include placing the first source and the third source at a same potential. In a particular embodiment, the first source can be electrically insulated from the second source. | 10-09-2008 |
20090016140 | DYNAMIC VOLTAGE ADJUSTMENT FOR MEMORY - A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit. | 01-15-2009 |
20110107160 | TIME-BASED TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A MEMORY ARRAY - A technique for detecting an imminent read failure in a memory array includes determining a first incident count for a memory array that does not exhibit an uncorrectable error correcting code (ECC) read during an array integrity check. In this case, the first incident count corresponds to an initial number of ECC corrections that are performed when the array integrity check of the memory array initially fails. The technique also includes determining a current count for the memory array when the memory array does not exhibit an uncorrectable ECC read during subsequent array integrity checks. In this case, the current count corresponds to a subsequent number of error correcting code (ECC) corrections required during the subsequent array integrity checks. An indication of an imminent read failure for the memory array is provided when the current count exceeds the first incident count by a predetermined amount. | 05-05-2011 |
20110107161 | THRESHOLD VOLTAGE TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A MEMORY ARRAY - A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level. | 05-05-2011 |
20150067314 | SECURE FIRMWARE FLASH CONTROLLER - A microcontroller that includes a secure firmware flash controller is provided. The secure firmware flash controller utilizes a hardware assisted boot sequence that performs a firmware code validation. If the firmware code fails validation for any reason, the firmware flash controller locks out access to the firmware RAM and firmware flash controller, and passes control back to the microcontroller for further measures that are protected by security protocols on the microcontroller. | 03-05-2015 |