Jin-Fu
Jin-Fu Chen, Taipei TW
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20110186335 | CIRCUIT BOARD WITH HEAT DISSIPATING STRUCTURE AND MANUFACTURING METHOD THEREOF - The circuit board with a heat dissipating structure is provided. A first grounding conductor layer is formed on a first surface of a substrate. A first insulting layer is formed on the first grounding conductor layer and defines a number of circuit element pin openings and a plurality of heat dissipating openings therein so that the first grounding conductor layer is exposed from the circuit element pin openings and the heat dissipating openings. A number of solder balls are disposed in the circuit element pin openings and contacted with the first grounding conductor layer. A number of heat dissipating structures are disposed in the heat dissipating openings and contacted with the first grounding conductor layer. The heat dissipating structures and the solder balls have an identical material. The method for manufacturing the circuit board is also provided. | 08-04-2011 |
Jin-Fu Li, Pingzhen City TW
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20130326294 | 3-D Memory and Built-In Self-Test Circuit Thereof - A three-dimensional (3-D) memory includes: multiple memory dies, each having at least one memory bank and a built-in self-test (BIST) circuit; and a plurality of channels, for electrically connecting the memory dies. In a synchronous test, one of the memory dies is selected as a master die. The BIST circuit of the master die sends an enable signal via the channels to the memory dies under test. The BIST circuit in each of the memory dies is for testing memory banks on the same memory die or on different memory dies. | 12-05-2013 |
Jin-Fu Li, Taoyuan County TW
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20140325311 | HYBRID ERROR CORRECTION METHOD AND MEMORY REPAIR APPARATUS THEREOF - A hybrid error correction method and a memory repair apparatus thereof are provided for a dynamic random access memory (DRAM). The memory repair apparatus includes a mode register and a hybrid error correction code and redundancy (HEAR) module. When the DRAM enters a standby mode, the mode register switches the DRAM to be controlled by the HEAR module. The HEAR module generates parity data of the error correction code within a default refresh period. The HEAR module extends the refresh period of the DRAM and uses the parity data for error detection to locate a data retention error in the DRAM until the maximum allowable refresh period supported by the HEAR module is reached. Before the DRAM returns to a working mode from a standby mode, the HEAR module performs an error correction process according to fail bit data and writes corrected data into the DRAM. | 10-30-2014 |
Jin-Fu Lin, Tainan City TW
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20120268304 | SWITCHED-CAPACITOR CIRCUIT AND PIPELINED ANALOG-TO-DIGITAL CONVERTER - A switched-capacitor circuit which comprises a first sampling capacitor, a second sampling capacitor, an op-amp, a third capacitor, and a fourth capacitor is provided. The first sampling capacitor is disposed to sample an input signal in a sampling phase. The second sampling capacitor is disposed to sample the input signal in the sampling phase. Wherein, in a first amplify phase, the third capacitor stores an offset voltage of the op-amp, the fourth capacitor stores the electric charges which are flowed from the first sampling capacitor and the second sampling capacitor, and in a second amplify phase, the fourth capacitor gives the stored electric charges back to the first sampling capacitor and the second sampling capacitor. | 10-25-2012 |
20120280846 | SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER - A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first capacitor array, a first input capacitor, a first switch module, a second capacitor array, a second input capacitor, a second switch module, a comparator and a SAR controller. The SAR ADC is operated under sampling phases and amplifying phases many times to perform amplifying operations and ADC operations upon input signals to generate digital output data. In addition, because the SAR ADC has both an amplification function and an ADC function, a circuit utilizing the SAR ADC does not require an additional active PGA, and a power consumption of the circuit is decreased. | 11-08-2012 |
20130044014 | SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER WITH CAPACITOR MISMATCH CALIBRATION AND METHOD THEREOF - A capacitance mismatch calibrating method for a successive approximation register ADC which includes at least one array of capacitors is provided. The method includes the following steps: firstly, at least two compensating capacitors are configured. A capacitor from the array of capacitors is selected as a capacitor-under-test. Then, the terminal voltages on the terminals of the array of capacitors and on the terminals of the compensating capacitors are determined. A first comparison voltage is outputted based on the determined terminal voltages. Afterwards, a sequence of comparisons is controlled based on the first comparison voltage and a second comparison voltage to output a sequence of corresponding digital bits. Finally, a calibration value is calculated to calibrate the value of a capacitor-under-test according to the digital bits. | 02-21-2013 |
20130076554 | SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER - A SAR ADC, used for converting an analog input into an N-bit digital output in a conversion phase, includes: three comparators, each two capacitor sub-arrays, coupled to the three comparators respectively, wherein the two capacitor sub-arrays are used for sampling the analog input and providing two inputs for the corresponding comparator; and an SAR logic, coupled to the three comparators and the three capacitor arrays, for, in each conversion sub-phase, coupling two selected capacitors of each capacitor sub-array to a set of determined reference levels, coupling two capacitors, which were selected in a preceding conversion sub-phase, of each capacitor sub-array to a set of adjusted reference levels obtained based on a set of data outputted from the three comparators in a preceding conversion sub-phase, and then generating two bits of the N-bit digital output by encoding a set of data outputted from the three comparators. | 03-28-2013 |
20130285843 | MULTI-BIT PER CYCLE SUCCESSIVE APPROXIMATION REGISTER ADC - A main digital-to-analog converter (DAC) receives at least one input and generates an adjusted input. A SAR unit generates a code for controlling the main DAC based on a comparison output of a comparing unit that receives the adjusted input. A reference generator, under control of the generated code, generates at least one reference voltage, which is then forwarded to the comparing unit in each corresponding cycle for defining a search range of each cycle, wherein an absolute value of the reference voltage of a latter cycle is less than the reference voltage of a former cycle such that the search range of the latter cycle is smaller than the search range of the former cycle, and search ranges of all the cycles are centered at a base voltage. | 10-31-2013 |
20130321184 | SAR Assisted Pipelined ADC and Method for Operating the Same - A method for operating a SAR assisted pipelined ADC includes enabling a SAR ADC in a current stage circuit for converting an input analog voltage into a digital code during a first time interval, resetting an operational amplifier of an MDAC in the current stage circuit during the first time interval, maintaining the SAR ADC of the current stage circuit in an enabled state for outputting during a second time interval, and enabling the MDAC in the current stage circuit during the second time interval. The method also includes enabling the SAR ADC in the current stage circuit for sampling during a third time interval and connecting the output terminal of the MDAC in the current stage circuit to the input terminal of the next stage circuit during the third time interval. The first, second, and third time intervals are continuous and do not overlap each other. | 12-05-2013 |
Jin-Fu Lin, Taipei City TW
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20100004747 | Trans-Vertebral and Intra-Vertebral Plate and Fusion Cage Device for Spinal Interbody Fusion and Method of Operation - A trans-vertebral and intra-vertebral plate and a rectangular cage with a slot for the plate of spinal fixation device are for neutralizing intervertebral movement for the spinal interbody fusion. The rectangular cage with a vertical or oblique slot is inserted into the intervertebral space from the lateral or anterior side of the spinal column and then the plate is inserted through the slot of the cage and hammered into and buried inside two adjacent vertebral bodies, to achieve three-dimensional intervertebral fixation. | 01-07-2010 |
Jin-Fu Wang, Zhenjiang CN
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20100034793 | METHOD OF USING STROMA CELLS FROM CORD BLOOD TO EXPAND AND ENGRAFT NUCLEATED CELLS FROM CORD BLOOD - The invention features a method for expanding and engrafting nucleated cells, e.g., progenitor cells, such as hematopoietic cells, obtained from cord blood by co-culturing the nucleated cells with adherent stroma cells, e.g., mesenchymal stem/progenitor cells, also obtained from cord blood. | 02-11-2010 |
Jin-Fu Wang, Guangdong CN
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20140085535 | METHOD AND IMAGE PROCESSING APPARATUS FOR IDENTIFYING STATE OF MACRO BLOCK OF DE-INTERLACING COMPUTING - A method for identifying state of macro block of de-interlacing computing and an image processing apparatus are provided, the method is as follows. A video frame is divided into a plurality of regions, where each of the regions includes a plurality of macro blocks. Then, a basic threshold corresponding to each of the regions is provided according to a position of each of the regions in the video frame, and a first macro block is identified to be a first type macro block or a second type macro block according to the basic threshold corresponding to one of the regions where the first macro block of the macro blocks locates. Then, a corresponding de-interlacing computing step is performed on the first macro block according to an result that the first macro block is identified as the first type macro block or the second type macro block. | 03-27-2014 |
Jin-Fu Yeh, Taoyuan County TW
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20150194941 | POWER AMPLIFYING APPARATUS - A power amplifying apparatus is provided. The power amplifying apparatus includes a first substrate and N power amplifiers. The N power amplifiers are disposed on the first substrate, the power amplifiers respectively receives N input signals, wherein frequency bands of at least two of the inputs signals are different. And the power amplifiers respectively generate M output signals, wherein the N is a positive integer greater than 2, and M is a positive integer not equal to N. | 07-09-2015 |
Jin-Fu Yeh, Taipei TW
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20150214994 | THREE-DIMENSIONAL POWER AMPLIFIER ARCHITECTURE - The present disclosure provides a three-dimensional (3-D) transformer-based (TF-based) power amplifier architecture, including a power splitting plane having at least one input transformer-based circuit; and a power combining plane having at least one output transformer-based circuit. The power splitting plane includes at least one input transmission line, at least one input transformer and an input terminal. Moreover, the power combining plane includes at least one output transmission line, at least one output transformer, at least one power amplifier-cell (PA-cell) and an output terminal. The power combining plane is vertically stacked, attached and electrically connected to the power splitting plane. Consequently, as compared with the existing 2-D power amplifiers, the 3-D transformer-based power amplifier architecture of the present disclosure is capable of achieving a symmetric and compact power distribution layout. Accordingly, the present disclosure further provides an integrated circuit layout for the 3-D TF-based power amplifier architecture. | 07-30-2015 |