Jin-Ha Park
Jin-Ha Park, Icheon-Si KR
Patent application number | Description | Published |
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20100109073 | FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A flash memory device includes a semiconductor substrate having a trench formed therein, the trench including a device isolation film, an oxide film formed over the semiconductor substrate including the trench, a nitride film pattern inserted into the oxide film and formed at a sidewall of the trench, and a polysilicon pattern formed over the oxide film including the nitride film pattern. A method for manufacturing a flash memory device includes forming a first oxide film over the semiconductor substrate including the trench, forming the nitride film pattern at the sidewall of the trench provided with the first oxide film and forming a second oxide film over the semiconductor substrate including the nitride film pattern, forming an oxide film pattern at a contact surface between the nitride film pattern and the semiconductor substrate and a side of the nitride film pattern by partially removing the first oxide film and the second oxide film formed over the bottom of the trench and the semiconductor substrate, and forming a third oxide film over the semiconductor substrate including the oxide film pattern to form the oxide cover film into which the nitride film pattern is inserted. | 05-06-2010 |
20100155820 | Flash memory device and manufacturing method of the same - A flash memory device may include a device isolation layer and an active area formed over a semiconductor substrate, a memory gate formed over the active area, and a control gate formed over the semiconductor substrate including the memory gate, wherein the active area, where a source contact is to be formed, has the same interval spacing as a bit line, and a common source line area, where the source contact is to be formed, has an impurity area connecting neighboring active areas. | 06-24-2010 |
Jin-Ha Park, Echeon-Si KR
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20080224137 | Image Sensor and Method for Manufacturing the Same - An image sensor and a method of manufacturing the same are provided. A metal wiring layer is formed on a semiconductor substrate including a circuit region, and first conductive layers are formed on the metal layer separated by a pixel isolation layer. An intrinsic layer is formed on the first conductive layers, and a second conductive layer is formed on the intrinsic layer. | 09-18-2008 |
20090140324 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing a flash memory device and a flash memory device in which a tunnel oxide layer and a first polysilicon pattern are formed on and/or over a semiconductor substrate. A second polysilicon pattern and a third polysilicon pattern are formed on and/or over a sidewall of the first polysilicon pattern and a dielectric layer and a polysilicon layer formed on and/or over the first, second and third polysilicon patterns. An etching process is performed to form a tunnel oxide layer pattern, a dielectric pattern, and a fourth polysilicon pattern. | 06-04-2009 |
20090146204 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a first poly layer over a semiconductor substrate, an IPD layer over the first poly layer, a second poly layer over the IPD layer, an oxide layer over a sidewall of the second poly layer, a first insulating layer over a sidewall of the oxide layer, and a second insulating layer over a sidewall of the first insulating layer. | 06-11-2009 |
Jin-Ha Park, Echeon-Sl KR
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20090140314 | FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Embodiments relate to a flash memory device and a method of manufacturing the same that may include a tunnel oxide layer on and/or over a semiconductor substrate having source and drain regions. The tunnel oxide layer may have a first width The flash memory device may include a first polysilicon pattern and a second polysilicon pattern on and/or over the tunnel oxide layer and a dielectric pattern on and/or over the tunnel oxide layer, where the first and second polysilicon patterns may be provided. It may also include a third polysilicon pattern on and/or over the dielectric pattern, the third polysilicon pattern having a second width, and a spacer formed on and/or over sidewalls of the first, second and third polysilicon patterns, the dielectric pattern and the tunnel oxide pattern. According to embodiments, the second width may be greater than the first width. | 06-04-2009 |
Jin-Ha Park, Gangnam-Gu KR
Patent application number | Description | Published |
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20090020833 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes forming first spacers formed of a TEOS layer and second spacers formed of a first nitride layer on sidewalls of a gate electrode formed on a semiconductor substrate, and then forming source/drain regions in the semiconductor substrate using the first and second spacers and the gate electrode as masks, and then removing the second spacers, and then depositing a second nitride layer on an entire surface of the semiconductor substrate, and then implanting ions into the second nitride layer to generate compressive stress, and then etching the second nitride layer to form barrier nitride layers on the side walls of the first spacers. Because the barrier nitride has compressive stress, it is possible to prevent the movement of mobile ions, minimize influence on charge loss and charge gain in a flash memory device, and enhance a retention characteristic. | 01-22-2009 |
20090026581 | FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method includes forming trenches in a semiconductor substrate by etching the semiconductor substrate; and then forming a first ion injection layer in sidewalls of the trenches at an active region of the semiconductor substrate; and then forming a second ion injection layer in a substantially horizontally extending surface of the active region located between the trenches; and then performing a threshold voltage adjusting implant on at least the active region, wherein the first ion injection layer and the second ion injection layer overlap at a portion of the active region to provide the overlapping portion with a higher doping concentration than a non-overlapping portion of the active region; and then forming a gate structure on the active region. Since the ion doping concentration of the surface of an active area between isolation layers is totally uniform, an electric current flows uniformly through the overall surface to prevent leakage current, to improve reliability, and to prolong lifespan of the flash memory device. | 01-29-2009 |