Patent application number | Description | Published |
20090085534 | WIDEBAND LOW DROPOUT VOLTAGE REGULATOR - Method and apparatus for regulating a supply voltage. Native NMOS source followers may be stacked and coupled to a supply a regulated voltage to a load. The gates of the native NMOS source followers are coupled to the outputs of internal regulators. The internal regulators may also contain stacked NMOS source followers. In an embodiment, the internal regulators may be supplied by a high voltage source, while the native NMOS source followers may be supplied by a low voltage source. In another embodiment, low-pass filters may filter the signal from the internal regulators to the NMOS source followers. In yet another embodiment, the gates of the source followers may be coupled to the sources of the transistors within the internal regulators. | 04-02-2009 |
20100026383 | DIRECT CURRENT (DC) OFFSET CORRECTION USING ANALOG-TO-DIGITAL CONVERSION - Techniques for reducing or eliminating DC (direct current) offset in transmitters are disclosed. An apparatus for DC offset reduction may include a converter, a digital engine, and a plurality of programmable current supplies. The converter is configured to provide digital representations of a plurality of DC currents associated, respectively, with a plurality of differential signal legs. The digital engine is configured to receive the digital representations and to produce instructions for generating compensating currents for the plurality of differential signal legs based on comparisons, respectively, between each of the digital representations and a calibration current. The programmable current supplies correspond, respectively, to the differential signal legs. The current supplies are configured to inject the compensating currents into the differential signal legs, respectively, to reduce DC offset between the differential signal legs, based upon the instructions. The instructions allow one-shot DC offset correction, instead of successive approximation for DC offset correction. | 02-04-2010 |
20100026393 | DRIVER AMPLIFIER HAVING A PROGRAMMABLE OUTPUT IMPEDANCE ADJUSTMENT CIRCUIT - A driver amplifier in an integrated circuit is suitable for driving a signal onto an output node and through an output terminal, and through a matching network to a power amplifier. A novel Programmable Output Impedance Adjustment Circuit (POIAC) within the integrated circuit is coupled to the output node and affects an output impedance looking into the output terminal. When the output impedance would otherwise change (for example, due to a driver amplifier power gain change), the POIAC adjusts how it loads the output node such that the output impedance remains substantially constant. The POIAC uses a series-connected inductor and capacitor L-C-R circuit to load the output node, thereby reducing the amount of capacitance and die area required to perform multi-band impedance matching with a power amplifier. Multi-band operation is accomplished by changing an effective capacitance in the L-C-R circuit depending on communication band information received by the POIAC. | 02-04-2010 |
20100120369 | RF TRANSCEIVER IC HAVING INTERNAL LOOPBACK CONDUCTOR FOR IP2 SELF TEST - An RF transceiver integrated circuit has a novel segmented, low parasitic capacitance, internal loopback conductor usable for conducting IP2 self testing and/or calibration. In a first novel aspect, the transmit mixer of the transceiver is a current mode output mixer. The receive mixer is a passive mixer that has a low input impedance. In the loopback mode, the transmit mixer drives a two tone current signal to the passive mixer via the loopback conductor. In a second novel aspect, only one quadrature branch of the transmit mixer is used to generate both tones required for carrying out an IP2 test. In a third novel aspect, a first calibration test is performed using one quadrature branch of the transmit mixer at the same time that a second calibration test is performed using the other quadrature branch, thereby reducing loopback test time and power consumption. | 05-13-2010 |
20130281042 | RECONFIGURABLE LNA FOR INCREASED JAMMER REJECTION - A reconfigurable LNA for increased jammer rejection is disclosed. An exemplary embodiment includes an LNA having a tunable resonant frequency, and a detector configured to output a control signal to tune the resonant frequency of the LNA to increase jammer suppression. An exemplary method includes detecting if a jammer is present, tuning a resonant frequency of an LNA away from the jammer to increase jammer rejection if the jammer is present, and tuning the resonant frequency of the LNA to a selected operating frequency if the jammer is not present. | 10-24-2013 |
20140162570 | RFIC CONFIGURATION FOR REDUCED ANTENNA TRACE LOSS - An RFIC configuration for reduced antenna trace loss is disclosed. In an exemplary embodiment, an apparatus includes a primary RFIC and a secondary RFIC that is configured to receive analog signals from at least two antennas. The secondary RFIC is configured to process selected analog signals received from at least one antenna to generate an analog output that is input to the primary RFIC. | 06-12-2014 |
20140256278 | SIMULTANEOUS SIGNAL RECEPTION WITH INTERSPERSED FREQUENCY ALLOCATION - Methods and circuits can down convert at least a first RF signal on a first path in a first frequency band to provide a first IF signal. A second RF signal on second path in a second frequency band can be down converted to provide a second IF signal. The first IF signal and the second IF signal are interspersed in the frequency domain, and the first frequency band is different from the second frequency band. A combiner can combine at least part of the first IF signal and the second IF signal to provide a combined signal on an output signal path for reception by a digital processing circuit. The first IF signal or second IF signal can be a Zero IF (ZIF), very low IF (VLIF), or Low IF (LIF) signal. | 09-11-2014 |
20140266886 | CONCURRENT MULTI-SYSTEM SATELLITE NAVIGATION RECEIVER WITH REAL SIGNALING OUTPUT - A global navigation satellite system (GNSS) receiver includes at least one GNSS antenna configured to receive input signaling from at least a first GNSS source and a second GNSS source; an in-phase/quadrature (I/Q) mixer coupled to the at least one GNSS antenna and configured to process the input signaling to obtain complex intermediate signaling; a first complex filter coupled to the I/Q mixer and configured to filter the complex intermediate signaling with respect to a first frequency range to obtain first real output signaling; a second complex filter coupled to the I/Q mixer and configured to filter the complex intermediate signaling with respect to a second frequency range to obtain second real output signaling; and a signal combiner coupled to the first and second complex filters and configured to generate combined real output signaling by combining the first real output signaling and the second real output signaling. | 09-18-2014 |
20140269853 | REUSING A SINGLE-CHIP CARRIER AGGREGATION RECEIVER TO SUPPORT NON-CELLULAR DIVERSITY - A wireless communication device configured for receiving multiple signals is described. The wireless communication device includes a single-chip carrier aggregation receiver architecture. The single-chip carrier aggregation receiver architecture includes a first antenna, a second antenna, a third antenna, a fourth antenna and a transceiver chip. The transceiver chip includes multiple carrier aggregation receivers. The single-chip carrier aggregation receiver architecture reuses at least one of the carrier aggregation receivers for secondary diversity. | 09-18-2014 |