Patent application number | Description | Published |
20110305064 | INTERFACE CONTROL FOR IMPROVED SWITCHING IN RRAM - A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell. | 12-15-2011 |
20110305065 | NON-VOLATILE VARIABLE CAPACITIVE DEVICE INCLUDING RESISTIVE MEMORY CELL - A non-volatile variable capacitive device includes a capacitor defined over a substrate, the capacitor having an upper electrode and a resistive memory cell having a first electrode, a second electrode, and a switching layer provided between the first and second electrodes. The resistive memory cell is configured to be placed in a plurality of resistive states according to an electrical signal received. The upper electrode of the capacitive device is coupled to the second electrode of the resistive memory cell. The resistive memory cell is a two-terminal device. | 12-15-2011 |
20110305066 | WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE - A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value. | 12-15-2011 |
20110317470 | RECTIFICATION ELEMENT AND METHOD FOR RESISTIVE SWITCHING FOR NON VOLATILE MEMORY DEVICE - A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided. | 12-29-2011 |
20120001146 | NANOSCALE METAL OXIDE RESISTIVE SWITCHING ELEMENT - A non-volatile memory device structure. The non-volatile memory device structure comprises a first electrode formed from a first metal material, a resistive switching element overlying the first electrode. The resistive switching element comprises a metal oxide material characterized by one or more oxygen deficient sites. The device includes a second electrode overlying the resistive switching layer, the second electrode being formed from a second metal material. The second electrode is made from a noble metal. The one or more oxygen deficient sites are caused to migrate from one of the first electrode or the second electrode towards the other electrode upon a voltage applied to the first electrode or the second electrode. The device can have a continuous change in resistance upon applying a continuous voltage ramp, suitable for an analog device. Alternatively, the device can have a sharp change in resistance upon applying the continuous voltage ramp, suitable for a digital device. | 01-05-2012 |
20120007035 | Intrinsic Programming Current Control for a RRAM - A resistive switching device. The device includes a substrate and a first dielectric material overlying a surface region of the substrate. The device includes a first electrode overlying the first dielectric material and an optional buffer layer overlying the first electrode. The device includes a second electrode structure. The second electrode includes at least a silver material. In a specific embodiment, a switching material overlies the optional buffer layer and disposed between the first electrode and the second electrode. The switching material comprises an amorphous silicon material in a specific embodiment. The amorphous silicon material is characterized by a plurality of defect sites and a defect density. The defect density is configured to intrinsically control programming current for the device. | 01-12-2012 |
20120015506 | TWO TERMINAL RESISTIVE SWITCHING DEVICE STRUCTURE AND METHOD OF FABRICATING - A method of forming a two terminal device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a first side region, and a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms an opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element. A top wiring material including a conductive material is formed overlying at lease the opening region such that the conductive material is in direct contact with the switching element. A second etching process is performed to form at least a top wiring structure. In a specific embodiment, the side region of the first structure including a first side region of the switching element is free from a contaminant conductive material from the second etching process. | 01-19-2012 |
20120043519 | DEVICE SWITCHING USING LAYERED DEVICE STRUCTURE - A resistive switching device. The device includes a first electrode comprising a first metal material overlying the first dielectric material and a switching material comprising an amorphous silicon material. The device includes a second electrode comprising at least a second metal material. In a specific embodiment, the device includes a buffer material disposed between the first electrode and the switching material. The buffer material provides a blocking region between the switching material and the first electrode so that the blocking region is substantially free from metal particles from the second metal material when a first voltage is applied to the second electrode. | 02-23-2012 |
20120074374 | CONDUCTIVE PATH IN SWITCHING MATERIAL IN A RESISTIVE RANDOM ACCESS MEMORY DEVICE AND CONTROL - A non-volatile memory device structure. The device structure includes a first electrode, a second electrode, a resistive switching material comprising an amorphous silicon material overlying the first electrode, and a thickness of dielectric material having a thickness ranging from 5 nm to 10 nm disposed between the second electrode and the resistive switching layer. The thickness of dielectric material is configured to electrically breakdown in a region upon application of an electroforming voltage to the second electrode. The electrical breakdown allows for a metal region having a dimension of less than about 10 nm by 10 nm to form in a portion of the resistive switching material. | 03-29-2012 |
20120074507 | INTEGRATION OF AN AMORPHOUS SILICON RESISTIVE SWITCHING DEVICE - An integrated circuit device. The integrated circuit device includes a semiconductor substrate having a surface region. A gate dielectric layer overlies the surface region of the substrate. The device includes a MOS device having a p+ active region. The p+ active region forms a first electrode for a resistive switching device. The resistive switching device includes an amorphous silicon switching material overlying the p+ active region and a metal electrode overlies the first metal conductor structure. The metal electrode includes a metal material, upon application of a positive bias to the metal electrode, forms a metal region in the amorphous silicon switching material. The MOS device provides for a select transistor for the integrated circuit device. | 03-29-2012 |
20120075907 | RESISTOR STRUCTURE FOR A NON-VOLATILE MEMORY DEVICE AND METHOD - A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value. | 03-29-2012 |
20120305879 | SWITCHING DEVICE HAVING A NON-LINEAR ELEMENT - A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold. | 12-06-2012 |
20120320660 | WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE - A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value. | 12-20-2012 |
20130122680 | RESISTOR STRUCTURE FOR A NON-VOLATILE MEMORY DEVICE AND METHOD - A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value. | 05-16-2013 |
20130148410 | NON-VOLATILE VARIABLE CAPACITIVE DEVICE INCLUDING RESISTIVE MEMORY CELL - A non-volatile variable capacitive device includes a capacitor defined over a substrate, the capacitor having an upper electrode and a resistive memory cell having a first electrode, a second electrode, and a switching layer provided between the first and second electrodes. The resistive memory cell is configured to be placed in a plurality of resistive states according to an electrical signal received. The upper electrode of the capacitive device is coupled to the second electrode of the resistive memory cell. The resistive memory cell is a two-terminal device. | 06-13-2013 |
20130234092 | THREE DIMENSION PROGRAMMABLE RESISTIVE RANDOM ACCESSED MEMORY ARRAY WITH SHARED BITLINE AND METHOD - A method of forming a non-volatile memory device. A substrate is provided and a first dielectric material forms overlying the substrate. A first polysilicon material is deposited overlying the first dielectric material. A second dielectric material is deposited overlying the first polysilicon material. A second polysilicon material is deposited overlying the second dielectric material. A third dielectric material is formed overlying the second polysilicon material. The third dielectric material, the second polysilicon material, the second dielectric material, and the first polysilicon material is subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material, a third wordline and associated with a third switching device, and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and overlies the amorphous silicon material and connected to a common bitline. | 09-12-2013 |
20130279240 | HETERO-SWITCHING LAYER IN A RRAM DEVICE AND METHOD - A non-volatile memory device structure includes first electrodes comprising conductive silicon-containing material, a plurality of resistive switching material stacks comprising first resistive switching material and second resistive switching material overlying the first electrode, wherein the first resistive switching material comprises a first resistance switching voltage and the second resistive switching material comprises a second resistance switching voltage less than the first amplitude, second electrodes comprising metal material overlying and electrically coupled to the plurality of resistive switching material stacks, wherein a plurality of memory elements are formed from the first plurality of electrodes, the plurality of resistive switching material stacks, and the second plurality of electrodes. | 10-24-2013 |
20130295744 | INTERFACE CONTROL FOR IMPROVED SWITCHING IN RRAM - A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell. | 11-07-2013 |
20130301341 | HERETO RESISTIVE SWITCHING MATERIAL LAYER IN RRAM DEVICE AND METHOD - A non-volatile memory device includes a first electrode, a resistive switching material stack overlying the first electrode. The resistive switching material stack comprising a first resistive switching material and a second resistive switching material. The second resistive switching material overlies the first electrode and the first resistive switching material overlying the second resistive switching material. The first resistive switching material is characterized by a first switching voltage having a first amplitude. The second resistive switching material is characterized by a second switching voltage having a second amplitude no greater than the first switching voltage. A second electrode comprising at least a metal material physically and electrically in contact with the first resistive switching material overlies the first resistive switching material. | 11-14-2013 |
20130308369 | SWITCHING DEVICE HAVING A NON-LINEAR ELEMENT - Method for a memory including a first, second, third and fourth cells include applying a read, program, or erase voltage, the first and second cells coupled to a first top interconnect, the third and fourth cells coupled to a second top interconnect, the first and third cells coupled to a first bottom interconnect, the second and fourth cells are to a second bottom interconnect, each cell includes a switching material overlying a non-linear element (NLE), the resistive switching material is associated with a first conductive threshold voltage, the NLE is associated with a lower, second conductive threshold voltage, comprising applying the read voltage between the first top and the first bottom electrode to switch the NLE of the first cell to conductive, while the NLEs of the second, third, and the fourth cells remain non-conductive, and detecting a read current across the first cell in response to the read voltage. | 11-21-2013 |
20140014890 | CONDUCTIVE PATH IN SWITCHING MATERIAL IN A RESISTIVE RANDOM ACCESS MEMORY DEVICE AND CONTROL - A non-volatile memory device structure. The device structure includes a first electrode, a second electrode, a resistive switching material comprising an amorphous silicon material overlying the first electrode, and a thickness of dielectric material having a thickness ranging from 5 nm to 10 nm disposed between the second electrode and the resistive switching layer. The thickness of dielectric material is configured to electrically breakdown in a region upon application of an electroforming voltage to the second electrode. The electrical breakdown allows for a metal region having a dimension of less than about 10 nm by 10 nm to form in a portion of the resistive switching material. | 01-16-2014 |
20140034898 | SWITCHING DEVICE HAVING A NON-LINEAR ELEMENT - A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold. | 02-06-2014 |
20140036605 | RESISTIVE SWITCHING FOR NON VOLATILE MEMORY DEVICE USING AN INTEGRATED BREAKDOWN ELEMENT - A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided. | 02-06-2014 |
20140145135 | SUB-OXIDE INTERFACE LAYER FOR TWO-TERMINAL MEMORY - Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can created comprising a non-stoichimetric sub-oxide that can be a combination of multiple silicon and/or silicon oxide layers with an aggregate chemical formula of SiO | 05-29-2014 |
20140158968 | NOBLE METAL / NON-NOBLE METAL ELECTRODE FOR RRAM APPLICATIONS - A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer. | 06-12-2014 |
20140185358 | RESISTIVE RANDOM ACCESS MEMORY WITH NON-LINEAR CURRENT-VOLTAGE RELATIONSHIP - Providing for fabrication, construction, and/or assembly of a resistive random access memory (RRAM) cell is described herein. The RRAM cell can exhibit a non-linear current-voltage relationship. When arranged in a memory array architecture, these cells can significantly mitigate sneak path issues associated with conventional RRAM arrays. | 07-03-2014 |
20140191180 | LOW TEMPERATURE P+ POLYCRYSTALLINE SILICON MATERIAL FOR NON-VOLATILE MEMORY DEVICE - A method of forming a non-volatile memory device. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the substrate. A first electrode structure is formed overlying the first dielectric material and a p+ polycrystalline silicon germanium material is formed overlying the first electrode structure. A p+ polycrystalline silicon material is formed overlying the first electrode structure using the polycrystalline silicon germanium material as a seed layer at a deposition temperature ranging from about 430 Degree Celsius to about 475 Degree Celsius without further anneal. The method forms a resistive switching material overlying the polycrystalline silicon material, and a second electrode structure including an active metal material overlying the resistive switching material. | 07-10-2014 |
20140192589 | REDUCED DIFFUSION IN METAL ELECTRODE FOR TWO-TERMINAL MEMORY - Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments. | 07-10-2014 |
20140233301 | RESISTIVE SWITCHING FOR NON VOLATILE MEMORY DEVICE USING AN INTEGRATED BREAKDOWN ELEMENT - A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided. | 08-21-2014 |
20140264226 | INTEGRATION OF AN AMORPHOUS SILICON RESISTIVE SWITCHING DEVICE - An integrated circuit device. The integrated circuit device includes a semiconductor substrate having a surface region. A gate dielectric layer overlies the surface region of the substrate. The device includes a MOS device having a p+ active region. The p+ active region forms a first electrode for a resistive switching device. The resistive switching device includes an amorphous silicon switching material overlying the p+ active region and a metal electrode overlies the first metal conductor structure. The metal electrode includes a metal material, upon application of a positive bias to the metal electrode, forms a metal region in the amorphous silicon switching material. The MOS device provides for a select transistor for the integrated circuit device. | 09-18-2014 |
20140264236 | CONTROLLING ON-STATE CURRENT FOR TWO-TERMINAL MEMORY - Provision of fabrication, construction, and/or assembly of a memory device including a two-terminal memory portion is described herein. The two-terminal memory device fabrication can provide enhanced capabilities in connection with precisely tuning on-state current over a greater possible range. | 09-18-2014 |
20140264238 | SCALING OF FILAMENT BASED RRAM - A solid state memory comprises a top electrode, a bottom electrode and an insulating switching medium that is disposed at a thickness based on a predetermined function. The insulating switching medium generates a conduction path in response to an electric signal applied to the device. The thickness of the insulating switching medium is a function of a filament width of the conduction path and operates to prevent rupture of a semi-stable region. The semi-stable region maintains filament structure over time and does not degrade into retention failure. The solid state memory can comprise one or more conducting layers that can operate to control the conductance at an on-state of the memory and offer oxygen vacancies or metal ions to the switching medium. The function of the thickness of the insulating switching medium can vary depending upon the number of conduction layers disposed at the insulating switching medium. | 09-18-2014 |
20140264250 | LOW TEMPERATURE IN-SITU DOPED SILICON-BASED CONDUCTOR MATERIAL FOR MEMORY CELL - Providing for two-terminal memory cell structures and fabrication that can be achieved with a relatively low temperature process(es) is described herein. By way of example, disclosed two-terminal memory cells can be formed at least in part as a continuous deposition, potentially yielding improved efficiency in manufacturing. Furthermore, various embodiments can be compatible with some existing complementary metal oxide semiconductor fabrication processes, reducing or avoiding retooling overhead that might be associated with modifying existing fabrication processes in favor of other two-terminal memory cell fabrication techniques. | 09-18-2014 |
20140268998 | RRAM WITH DUAL MODE OPERATION - A two-terminal memory cell comprises a dual mode of operation in a unipolar mode and bipolar mode for a programming or On-state and for an erase or Off-state of the cell. The two-terminal memory cell is field programmable and can be flexibly designed or integrated into existing architecture. The two-terminal memory comprises a first electrode layer and a second electrode layer with a switching layer disposed between that has an electrical insulator material. A semiconductor layer is disposed between the switching layer and at least one of the first electrode or the second electrode. The switching layer generates a conductive path that is configured to be in a program state and an erase state, based on a bipolar mode and a unipolar mode. | 09-18-2014 |
20140269002 | TWO-TERMINAL MEMORY WITH INTRINSIC RECTIFYING CHARACTERISTIC - Providing for two-terminal memory having an inherent rectifying characteristic(s) is described herein. By way of example, the two-terminal memory can be a resistive switching device having one or more “on” states and an “off” state, to facilitate storage of digital information. A conductive filament can be electrically isolated from an electrode of the two-terminal memory by a thin tunneling layer, which permits a tunneling current for voltages greater in magnitude than a positive rectifying voltage or a negative rectifying voltage. The two-terminal memory cell can therefore have high resistance to small voltages, mitigating leakage currents in an array of the two-terminal memory cells. In addition, the memory cell can be conductive above a rectifying voltage, enabling reading of the memory cell in response to a suitable read bias, and erasing of the memory cell in response to a suitable negative erase bias. | 09-18-2014 |
20140312296 | THREE-DIMENSIONAL OBLIQUE TWO-TERMINAL MEMORY WITH ENHANCED ELECTRIC FIELD - Providing for three-dimensional memory cells having enhanced electric field characteristics is described herein. By way of example, a two-terminal memory cell can be constructed from a layered stack of materials, where respective layers are arranged along a direction that forms a non-zero angle to a normal direction of a substrate surface upon which the layered stack of materials is constructed. In some aspects, the direction can be orthogonal to or substantially orthogonal to the normal direction. In other aspects, the direction can be less than orthogonal to the normal direction. Where an internal angle of the memory cell forms a non-orthogonal angle, an enhanced electric field or current density can result, providing improved switching times and memory performance. | 10-23-2014 |
20140328108 | WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE - A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value. | 11-06-2014 |
20150021538 | DEVICE SWITCHING USING LAYERED DEVICE STRUCTURE - A resistive switching device. The device includes a first electrode comprising a first metal material overlying the first dielectric material and a switching material comprising an amorphous silicon material. The device includes a second electrode comprising at least a second metal material. In a specific embodiment, the device includes a buffer material disposed between the first electrode and the switching material. The buffer material provides a blocking region between the switching material and the first electrode so that the blocking region is substantially free from metal particles from the second metal material when a first voltage is applied to the second electrode. | 01-22-2015 |
20150102281 | SWITCHING DEVICE HAVING A NON-LINEAR ELEMENT - A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold. | 04-16-2015 |
20150144863 | RESISTIVE MEMORY DEVICE AND FABRICATION METHODS - A method for forming a resistive memory device includes providing a substrate comprising a first metal material, forming a conductive silicon-bearing layer on top of the first metal material, wherein the conductive silicon-bearing layer comprises an upper region and a lower region, and wherein the lower region is adjacent to the first metal material, forming an amorphous layer from the upper region of the conductive silicon-bearing layer, and disposing an active metal material above the amorphous layer. | 05-28-2015 |
20150155480 | GUIDED PATH FOR FORMING A CONDUCTIVE FILAMENT IN RRAM - A method of forming a non-volatile memory device, includes forming a first electrode above a substrate, forming a dielectric layer overlying the first electrode, forming an opening structure in a portion of the dielectric layer to expose a surface of the first electrode having an aspect ratio, forming a resistive switching material overlying the dielectric layer and filling at least a portion of the opening structure using a deposition process, the resistive switching material having a surface region characterized by a planar region and an indent structure, the indent structure overlying the first electrode, maintaining a first thickness of resistive switching material between the planar region and the first electrode, maintaining a second thickness of resistive switching material between the indent structure and the first electrode, wherein the first thickness is larger than the second thickness, and forming a second electrode overlying the resistive switching material including the indent structure. | 06-04-2015 |
20150188051 | THREE DIMENSION PROGRAMMABLE RESISTIVE RANDOM ACCESSED MEMORY ARRAY WITH SHARED BITLINE AND METHOD - A method of forming a non-volatile memory device. The method forms a vertical stack of first polysilicon material and a second polysilicon material layer isolated by a dielectric material. The polysilicon material layers and the dielectric material are subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material layer, and a third wordline associated with a third switching device and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and connects to a common bitline. | 07-02-2015 |
20150200362 | TWO TERMINAL RESISTIVE SWITCHING DEVICE STRUCTURE AND METHOD OF FABRICATING - A semiconductor device having a memory device includes a semiconductor substrate, a first dielectric layer disposed above the semiconductor substrate, a first adhesion layer disposed upon the first dielectric layer, a bottom wiring metal disposed upon the first adhesion layer, a first barrier layer disposed upon the bottom wiring metal, a resistive switching material disposed in electrical contact with the first barrier layer, wherein the resistive switching material comprises a silicon material having a plurality of defect regions, a conductive metal material disposed upon the resistive switching material, wherein the conductive metal material comprises a plurality of conductive metal particles, a second barrier layer disposed upon the conductive metal material, a top wiring metal disposed upon the second barrier layer, and wherein at least some of the plurality of conductive metal particles are removably disposed in defect regions from the plurality of defect regions in the resistive switching material. | 07-16-2015 |
20150228334 | MEMORY ARRAY ARCHITECTURE WITH TWO-TERMINAL MEMORY CELLS - A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor. | 08-13-2015 |
20150228894 | LOW TEMPERATURE DEPOSITION FOR SILICON-BASED CONDUCTIVE FILM - Providing for low temperature deposition of silicon-based electrical conductor for solid state memory is described herein. In various disclosed embodiments, the silicon-based conductor can form an electrode of a memory cell, an interconnect between conductive components of an electronic device, a conductive via, a wire, and so forth. Moreover, the silicon-based electrical conductor can be formed as part of a monolithic process incorporating complementary metal oxide semiconductor (CMOS) device fabrication. In particular embodiments, the silicon-based electrical conductor can be a p-type silicon germanium compound, that is activated upon deposition at temperatures compatible with CMOS device fabrication. | 08-13-2015 |
20150263069 | SELECTOR DEVICE FOR TWO-TERMINAL MEMORY - Providing for solid state memory having a non-linear current-voltage (I-V) response is disclosed herein. By way of example, the subject disclosure provides a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array. | 09-17-2015 |
20150340406 | RESISTIVE MEMORY ARCHITECTURE AND DEVICES - Providing a high-density two-terminal memory architecture(s) having performance benefits of two-terminal memory and relatively low fabrication cost, is described herein. By way of example, the two-terminal memory architecture(s) can be constructed on a substrate, in various embodiments, and comprise two-terminal memory cells formed within conductive layer recess structures of the memory architecture. In one embodiment, a conductive layer recess can be created as a horizontal etch in conjunction with a vertical via etch. In another embodiment, the conductive layer recess can be patterned for respective conductive layers of the two-terminal memory architecture. | 11-26-2015 |
20150357567 | RESISTIVE SWITCHING FOR NON VOLATILE MEMORY DEVICE USING AN INTEGRATED BREAKDOWN ELEMENT - A method of suppressing propagation of leakage current in an array of switching devices. The method includes providing a dielectric breakdown element integrally and serially connected to a switching element within each of the switching device. A read voltage (for example) is applied to a selected cell. The propagation of leakage current is suppressed by each of the dielectric breakdown element in unselected cells in the array. The read voltage is sufficient to cause breakdown in the selected cells but insufficient to cause breakdown in the serially connected, unselected cells in a specific embodiment. Methods to fabricate of such devices and to program, to erase and to read the device are provided. | 12-10-2015 |
20160005461 | SENSING A NON-VOLATILE MEMORY DEVICE UTILIZING SELECTOR DEVICE HOLDING CHARACTERISTICS - Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory. | 01-07-2016 |
Patent application number | Description | Published |
20100188105 | CAPACITANCE-TO-VOLTAGE INTERFACE CIRCUIT, AND RELATED OPERATING METHODS - A capacitance-to-voltage interface circuit is utilized to obtain a voltage corresponding to a detected capacitance differential, which may be associated with the operation of a capacitive sensing cell. The interface circuit includes a capacitive sensing cell, an operational amplifier adapted for selective coupling to the capacitive sensing cell, a feedback capacitor for the operational amplifier, a load capacitor for the operational amplifier, and a switching architecture associated with the capacitive sensing cell, the operational amplifier, the feedback capacitor, and the load capacitor. During use, the switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases. The different operational phases enable the single operational amplifier to be used for both capacitance-to-voltage conversion and voltage amplification. | 07-29-2010 |
20100188107 | CAPACITANCE-TO-VOLTAGE INTERFACE CIRCUIT WITH SHARED CAPACITOR BANK FOR OFFSETTING AND ANALOG-TO-DIGITAL CONVERSION - A capacitance-to-voltage interface circuit includes a capacitive sensing circuit, an amplification circuit adapted for selective coupling to the capacitive sensing circuit, a capacitor bank comprising a plurality of binary-weighted capacitors, and a switching architecture associated with the capacitive sensing circuit, the amplification circuit, and the capacitor bank. The switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases, including an amplification phase and an analog-to-digital conversion phase. During the amplification phase, the capacitor bank is utilized for offsetting capacitance of the amplification circuit. During the analog-to-digital conversion phase, the capacitor bank is utilized in a successive approximation register. | 07-29-2010 |
20100188278 | CHARGE REDISTRIBUTION SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER AND RELATED OPERATING METHOD - The analog-to-digital converter provided herein includes a capacitor bank comprising a plurality of binary-weighted capacitors, an operational amplifier having an inverting input node, a noninverting input node coupled to analog ground, and an output node, a reset switch, and an input switch. The reset switch is located between the capacitor bank and the operational amplifier, and it selectively couples the capacitor bank to the inverting input node. The input switch has its common terminal coupled to the capacitor bank, and the input switch selectively couples the capacitor bank to either an analog input voltage, a floating terminal, or analog ground. The capacitor bank includes N binary-weighted capacitors and one balacing capacitor that has a unit capacitance. During operation, the analog-to-digital converter generates an N-bit digital output and one polarity bit from the analog input voltage. | 07-29-2010 |
20110208460 | OFFSET ERROR AUTOMATIC CALIBRATION INTEGRATED CIRCUIT - An integrated circuit includes a transducer and transducer circuitry and additional elements useful in testing the transducer and transducer circuitry. A first power supply terminal and a second power supply terminal are for being directly connected to an external power supply terminal. A power bus is connected to the first power supply terminal. A logic function is for determining if the second power supply terminal is receiving power and if an automatic calibration test of the transducer and transducer circuitry has been run. An automatic calibration is for running an automatic calibration test on the transducer and transducer circuitry if the logic means determines that the second power supply terminal is receiving power and the automatic calibration test of the transducer and transducer circuitry has not been run. | 08-25-2011 |
20120105079 | CAPACITANCE-TO-VOLTAGE INTERFACE CIRCUITS - A capacitance-to-voltage interface circuit is utilized to obtain a voltage corresponding to a detected capacitance differential, which may be associated with the operation of a capacitive sensing cell. The interface circuit includes a capacitive sensing cell, an operational amplifier adapted for selective coupling to the capacitive sensing cell, a feedback capacitor for the operational amplifier, a load capacitor for the operational amplifier, and a switching architecture associated with the capacitive sensing cell, the operational amplifier, the feedback capacitor, and the load capacitor. During use, the switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases. The different operational phases enable the single operational amplifier to be used for both capacitance-to-voltage conversion and voltage amplification. | 05-03-2012 |
20130061649 | OFFSET ERROR AUTOMATIC CALIBRATION INTEGRATED CIRCUIT - An integrated circuit includes a transducer and transducer circuitry and additional elements useful in testing the transducer and transducer circuitry. A first power supply terminal and a second power supply terminal are for being directly connected to an external power supply terminal. A power bus is connected to the first power supply terminal. A logic function is for determining if the second power supply terminal is receiving power and if an automatic calibration test of the transducer and transducer circuitry has been run. An automatic calibration is for running an automatic calibration test on the transducer and transducer circuitry if the logic means determines that the second power supply terminal is receiving power and the automatic calibration test of the transducer and transducer circuitry has not been run. | 03-14-2013 |
20130283913 | MICROELECTROMECHANICAL SYSTEMS DEVICES AND METHODS FOR THE FABRICATION THEREOF - Embodiments of compact micro-electro-mechanical systems (MEMS) devices are provided, as are embodiments of methods for fabricating MEMS devices. In one embodiment, the MEMS device includes a substrate, a movable structure resiliently coupled to the substrate, and an anchored structure fixedly coupled to the substrate. The movable structure includes a first plurality of movable fingers, and a second plurality of movable fingers electrically isolated from and interspersed with the first plurality of movable fingers. The anchored structure includes fixed fingers interspersed with first and second pluralities of movable fingers in a capacitor-forming relationship. First and second interconnects are electrically coupled to the first and second pluralities of movable fingers, respectively. | 10-31-2013 |
20140253148 | CAPACITANCE-TO-VOLTAGE INTERFACE CIRCUITS - A capacitance-to-voltage interface circuit is utilized to obtain a voltage corresponding to a detected capacitance differential, which may be associated with the operation of a capacitive sensing cell. The interface circuit includes a capacitive sensing cell, an operational amplifier adapted for selective coupling to the capacitive sensing cell, a feedback capacitor for the operational amplifier, a load capacitor for the operational amplifier, and a switching architecture associated with the capacitive sensing cell, the operational amplifier, the feedback capacitor, and the load capacitor. During use, the switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases. The different operational phases enable the single operational amplifier to be used for both capacitance-to-voltage conversion and voltage amplification. | 09-11-2014 |
20150177775 | DIGITAL SAMPLE CLOCK GENERATOR, A VIBRATION GYROSCOPE CIRCUITRY COMPRISING SUCH DIGITAL SAMPLE CLOCK GENERATOR, AN ASSOCIATED APPARATUS, AN ASSOCIATED SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS - A digital sample clock generator for generating a sample clock signal from an input signal derived from a drive measurement voltage signal of a vibrating MEMS gyroscope is provided. | 06-25-2015 |
20150233995 | SYSTEM AND METHOD FOR EVALUATING A CAPACITIVE INTERFACE - A method of evaluating a capacitive interface including discharging the capacitive interface to a lower voltage, timing while applying a unit charge to the capacitive interface until a voltage of the capacitive interface rises to a reference voltage and determining a corresponding charge time value, charging the capacitive interface to an upper voltage that is greater than the reference voltage, and timing while removing the unit charge from the capacitive interface until a voltage of the capacitive interface falls to the reference voltage and determining a corresponding discharge time value. The charge and discharge time values may be used to evaluate the capacitive interface by determining capacitance and leakage current. The time values may be determined using a counter. A capacitive interface evaluation system for evaluating the capacitive interface may include a charge circuit, a comparator, a counter and a controller. | 08-20-2015 |
20150260785 | METHOD FOR TESTING INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT CONFIGURED TO FACILITATE PERFORMING SUCH A METHOD - An integrated circuit, such as for example an application specific integrated circuit, as well as a method of testing such a circuit, are disclosed herein. In one example embodiment, the integrated circuit includes a plurality of pins including a power pin, a ground pin, and a first communication pin, a test mode circuit, and a communication circuit. The integrated circuit additionally includes a first switch connected to the first communication pin, where the first switch is configured to couple the first communication pin to either the test mode circuit or the communication circuit. The integrated circuit further includes a control circuit coupled to the first switch and configured to control whether the first switch is operated to couple the first communication pin to the test mode circuit or to the communication circuit based upon or in response to an operating mode. | 09-17-2015 |