Patent application number | Description | Published |
20100025479 | Doped Implant Monitoring for Microchip Tamper Detection - A method and apparatus include conductive material doped within a microchip that accumulates a detectable charge in the presence of ions. Such ions may result from a focused ion beam or other unwelcome technology exploitation effort. Circuitry sensing the charge buildup in the embedded, doped material may initiate a defensive action intended to defeat the tampering operation. | 02-04-2010 |
20100026326 | Resistance Sensing for Defeating Microchip Exploitation - A method, program product and apparatus include resistance structures positioned proximate security sensitive microchip circuitry. Alteration in the position, makeup or arrangement of the resistance structures may be detected and initiate an action for defending against a reverse engineering or other exploitation effort. The resistance structures may be automatically and selectively designated for monitoring. Some of the resistance structures may have different resistivities. The sensed resistance may be compared to an expected resistance, ratio or other resistance-related value. The structures may be intermingled with false structures, and may be overlapped or otherwise arranged relative to one another to further complicate unwelcome analysis. | 02-04-2010 |
20100026336 | FALSE CONNECTION FOR DEFEATING MICROCHIP EXPLOITATION - An integrated circuit assembly and associated method of detecting microchip tampering may include multiple connections in electrical communication with a conductive layer. Defensive circuitry may inhibit analysis of the microchip where a connection no longer connects to the conductive layer. The defensive circuitry may similarly be initiated where a connection unintended to be in electrical communication with the conductive layer is nonetheless connected. | 02-04-2010 |
20100026337 | Interdependent Microchip Functionality for Defeating Exploitation Attempts - An integrated circuit assembly comprising a microchip that shares an interdependent function with a second, stacked microchip. Alternation of the physical arrangement or functionality of the microchips may initiate a defense action intended to protect security sensitive circuitry associated with one of the microchips. The microchips may communicate using through-silicon vias or other interconnects. | 02-04-2010 |
20100308413 | 3-D SINGLE GATE INVERTER - A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions. | 12-09-2010 |
20110013445 | Bias Temperature Instability-Influenced Storage Cell - In a method of using a memory cell employing a field effect transistor (FET), the FET is heated to a first temperature sufficient to support bias temperature instability in the FET. The bit line is driven to a high voltage state. The word line is driven to a predetermined voltage state that causes bias temperature instability in the FET. The temperature, the high voltage state on the bit line and the predetermined voltage state on the word line are maintained for an amount of time sufficient to change a threshold voltage of the FET to a state where a desired data value is stored on the FET. The FET is cooled to a second temperature that is cooler than the first temperature after the amount of time has expired. | 01-20-2011 |
20110059583 | 3-D Single Gate Inverter - A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions. | 03-10-2011 |
20110172984 | EFFICIENCY OF STATIC CORE TURN-OFF IN A SYSTEM-ON-A-CHIP WITH VARIATION - A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off. | 07-14-2011 |
20110173432 | RELIABILITY AND PERFORMANCE OF A SYSTEM-ON-A-CHIP BY PREDICTIVE WEAR-OUT BASED ACTIVATION OF FUNCTIONAL COMPONENTS - A processor-implemented method for determining aging of a processing unit in a processor the method comprising: calculating an effective aging profile for the processing unit wherein the effective aging profile quantifies the effects of aging on the processing unit; combining the effective aging profile with process variation data, actual workload data and operating conditions data for the processing unit; and determining aging through an aging sensor of the processing unit using the effective aging profile, the process variation data, the actual workload data, architectural characteristics and redundancy data, and the operating conditions data for the processing unit. | 07-14-2011 |
20110298052 | Vertical Stacking of Field Effect Transistor Structures for Logic Gates - A vertical structure is formed upon a semiconductor substrate. The vertical structure comprises four dielectric layers parallel to a top surface of the semiconductor substrate and three conducting layers, one conducting layer between each vertically adjacent dielectric layer. A first FET (field effect transistor) and a third FET are arranged parallel to the top surface of the semiconductor and a second FET is arranged orthogonal to the top surface of the semiconductor. All three FETs are independently controllable. The first conducting layer is a gate electrode of the first FET; the second conducting layer is a gate electrode of the second FET, and the third conducting layer is the gate electrode of the third FET. | 12-08-2011 |
20110304350 | Mask Alignment, Rotation and Bias Monitor Utilizing Threshold Voltage Dependence - The present invention provides a method and apparatus for measuring alignment, rotation and bias of mask layers in semiconductor manufacturing by examining threshold voltage variation. | 12-15-2011 |
20120032274 | Vertically Stacked FETs With Series Bipolar Junction Transistor - Vertically stacked Field Effect Transistors (FETs) are created on a vertical structure formed on a semiconductor substrate where a first FET and a second FET are controllable independently. A bipolar junction transistor is connected between and in series with the first FET and the second FET, the bipolar junction transistor may be controllable independently of the first and second FET. | 02-09-2012 |
20120126330 | Enhanced Thin Film Field Effect Transistor Integration into Back End of Line - A semiconductor chip has self aligned (where a gate electrode and associated spacers define the source/drain implant with respect to the gate electrode) Field Effect Transistors (FETs) in a back end of the line (BEOL) portion of the semiconductor chip. The FETs are used to make buffer circuits in the BEOL to improve delay and signal integrity of long signal paths on the semiconductor chip. | 05-24-2012 |
20120146711 | Power Domain Controller With Gated Through Silicon Via Having FET With Horizontal Channel - A semiconductor chip has a gated through silicon via (TSVG). The TSVG may be switched so that the TSVG can be made conducting or non-conducting. The semiconductor chip may be used between a lower level semiconductor chip and a higher semiconductor chip to control whether a voltage supply on the lower level semiconductor chip is connected to or disconnected from a voltage domain in the upper level semiconductor chip. The TSVG comprises an FET controlled by the lower level chip as a switch. | 06-14-2012 |
20120175624 | IMPLEMENTING VERTICAL SIGNAL REPEATER TRANSISTORS UTILIZING WIRE VIAS AS GATE NODES - A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor. | 07-12-2012 |
20120175626 | IMPLEMENTING SEMICONDUCTOR SOC WITH METAL VIA GATE NODE HIGH PERFORMANCE STACKED TRANSISTORS - A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node. | 07-12-2012 |
20120211829 | FIELD-EFFECT TRANSISTOR AND METHOD OF CREATING SAME - A field-effect transistor has a gate, a source, and a drain. The gate has a via extending through a semiconductor chip substrate from one surface to an opposite surface of the semiconductor chip substrate. The source has a first toroid of ion dopants implanted in the semiconductor chip substrate surrounding one end of the via on the one surface of the semiconductor chip substrate. The drain has a second toroid of ion dopants implanted in the semiconductor chip substrate surrounding an opposite end of the via on the opposite surface of the semiconductor chip substrate. | 08-23-2012 |
20120216301 | IMPLEMENTING HACKING DETECTION AND BLOCK FUNCTION AT INDETERMINATE TIMES WITH PRIORITIES AND LIMITS - A method and circuits for implementing a hacking detection and block function at indeterminate times, and a design structure on which the subject circuit resides are provided. A circuit includes an antenna wrapped around a dynamic bus inside circuitry to be protected. The antenna together with the dynamic bus node is designed so an average bus access activates a field effect transistor (FET) that is connected to a capacitor. The FET drains the capacitor in a specified number of activations by the antenna. The capacitor has a leakage path to a voltage supply rail VDD that charges the capacitor back high after a time, such as ten to one hundred cycles, of the dynamic bus being quiet. The capacitor provides a hacking detect signal for temporarily blocking operation of the circuitry to be protected responsive to determining that the dynamic bus is more active than functionally expected. | 08-23-2012 |
20120267697 | eDRAM HAVING DYNAMIC RETENTION AND PERFORMANCE TRADEOFF - A semiconductor chip has an embedded dynamic random access memory (eDRAM) in an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM deep trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. Retention time and performance of the eDRAM is controlled by applying a voltage to the independently voltage controlled silicon region. | 10-25-2012 |
20120267752 | INDEPENDENTLY VOLTAGE CONTROLLED VOLUME OF SILICON ON A SILICON ON INSULATOR CHIP - A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide. | 10-25-2012 |
20120268160 | IMPLEMENTING TEMPORARY DISABLE FUNCTION OF PROTECTED CIRCUITRY BY MODULATING THRESHOLD VOLTAGE OF TIMING SENSITIVE CIRCUIT - A method and circuits for implementing a temporary disable function at indeterminate times of circuitry to be protected in a semiconductor chip, such as in an integrated circuit or a system on a chip (SOC) by modulating threshold voltage shifts of a timing sensitive circuit, and a design structure on which the subject circuit resides are provided. The timing sensitive circuit is designed to be sensitive to threshold-voltage shifts and is placed over an independently voltage controlled silicon region. Upon startup, the independently voltage controlled silicon region is grounded, and then is left floating. Each time a hack attempt or predefined functional oddity is detected, charge is applied onto the independently voltage controlled silicon region. After a defined charge has accumulated, the device threshold voltages in the timing sensitive circuit above the independently voltage controlled silicon region are modulated causing the timing-sensitive circuit to fail. | 10-25-2012 |
20120268195 | IMPLEMENTING eFUSE CIRCUIT WITH ENHANCED eFUSE BLOW OPERATION - A method and an eFuse circuit for implementing with enhanced eFuse blow operation without requiring a separate high current and high voltage supply to blow the eFuse, and a design structure on which the subject circuit resides are provided. The eFuse circuit includes an eFuse connected to a field effect transistor (FET) operatively controlled during a sense mode and a blow mode for sensing and blowing the eFuse. The eFuse circuit is placed over an independently voltage controlled silicon region. During a sense mode, the independently voltage controlled silicon region is grounded providing an increased threshold voltage of the FET. During a blow mode, the independently voltage controlled silicon region is charged to a voltage supply potential. The threshold voltage of the FET is reduced by the charged independently voltage controlled silicon region for providing enhanced FET blow function. | 10-25-2012 |
20130001676 | THROUGH SILICON VIA DIRECT FET SIGNAL GATING - A system comprises a first integrated circuit (IC) chip that includes a first electronic component; a second IC chip that includes a second electronic component; a through silicon via (TSV) in the second IC chip that electrically couples the first electronic component to the second electronic component; and a signal gating transistor that fully occludes the TSV. | 01-03-2013 |
20130020712 | IMPLEMENTING INTEGRATED CIRCUIT MIXED DOUBLE DENSITY AND HIGH PERFORMANCE WIRE STRUCTURE - A method and structures are provided for implementing an integrated circuit with an enhanced wiring structure of mixed double density and high performance wires in a common plane. A wiring structure includes a first wire having a first plane and a first via to a second wire in a second plane having a second via and a third wire having the first plane with height equal to the first wire and the first via, and a third via having a height equal to the second wire and the second via. | 01-24-2013 |
20130043544 | STRUCTURE HAVING THREE INDEPENDENT FINFET TRANSISTORS - A semiconductor chip has a FinFET structure with three independently controllable FETs on a single fin. The three FETs are connected in parallel so that current will flow between a common source and a common drain if one or more of the three independently controllable FETs is turned on. The three independently controllable FETs may be used in logic gates. | 02-21-2013 |
20130082268 | IMPLEMENTING VERTICAL SIGNAL REPEATER TRANSISTORS UTILIZING WIRE VIAS AS GATE NODES - A method and structures are provided for implementing vertical transistors utilizing wire vias as gate nodes. The vertical transistors are high performance transistors fabricated up in the stack between the planes of the global signal routing wire, for example, used as vertical signal repeater transistors. An existing via or a supplemental vertical via between wire planes provides both an electrical connection and the gate node of the novel vertical transistor. | 04-04-2013 |
20130126881 | IMPLEMENTING SEMICONDUCTOR SOC WITH METAL VIA GATE NODE HIGH PERFORMANCE STACKED TRANSISTORS - A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node. | 05-23-2013 |
20130146992 | DEEP TRENCH EMBEDDED GATE TRANSISTOR - A semiconductor device includes a source extending into a surface of a substrate, a drain extending into the surface of the substrate, and an embedded gate in the substrate extending from the source to the drain. | 06-13-2013 |
20130263075 | UTILIZING GATE PHASES FOR CIRCUIT TUNING - Implementing circuit tuning post design of an integrated circuit utilizing gate phases. Each phase includes a designation of one of a slow phase and a fast phase. During the circuit design phase, each device is given a phase designation based upon expected performance of the device in the circuit. If the device is expected to be in a critical path or has a minimum timing slack, the device is placed on the fast phase. If the device is not in a critical path or has excess timing slack the device is placed on the slow phase. | 10-03-2013 |
20130277798 | Implementing Semiconductor Signal-Capable Capacitors with Deep Trench and TSV Technologies - A method and structures are provided for implementing semiconductor signal-capable capacitors with deep trench and Through-Silicon-Via (TSV) technologies. A deep trench N-well structure is formed and an implant is provided in the deep trench N-well structure with a TSV formed in a semiconductor chip. At least one angled implant is created around the TSV in a semiconductor chip. The TSV is surrounded with a dielectric layer and filled with a conducting material which forms one electrode of the capacitor. A connection is made to one implant forming a second electrode to the capacitor. | 10-24-2013 |
20130292755 | IMPLEMENTING EDRAM STACKED FET STRUCTURE - A method and circuit for implementing an embedded dynamic random access memory (eDRAM), and a design structure on which the subject circuit resides are provided. The embedded dynamic random access memory (eDRAM) circuit includes a stacked field effect transistor (FET) and capacitor. The capacitor is fabricated directly on top of the FET to build the eDRAM. | 11-07-2013 |
20130313441 | Soft Error Detection - An apparatus includes a first radiation detector to generate a first signal when a first radiation level is exceeded and a second radiation detector to generate a second signal when a second radiation level is exceeded. The second radiation level is greater than the first radiation level. A first circuit is susceptible to soft errors at the first radiation level and a second circuit is susceptible to soft errors at the second radiation level. A control unit may suspend use of the first circuit and activate use of the second circuit if the first signal is received and the second signal is not received. The first and second circuits may be memory cells or logic circuits. | 11-28-2013 |
20130328159 | IMPLEMENTING ISOLATED SILICON REGIONS IN SILICON-ON-INSULATOR (SOI) WAFERS USING BONDED-WAFER TECHNIQUE - Methods and structures are provided for implementing independently voltage controlled isolated silicon regions under a buried oxide layer for biasing field effect transistors above the buried oxide layer on Silicon-on-Insulator (SOI) wafers. Using a bonded-wafer technique, a first bulk substrate wafer is bonded with a second wafer providing a buried oxide (BOX) layer under a transistor silicon layer creating an SOI wafer. An independently voltage controlled isolated silicon region is created in the created SOI wafer beneath the BOX layer. The transistor silicon layer is polished to a desired thickness, and normal processing is continued with transistors and desired circuits placed over the isolated silicon region. A contact is formed through the transistor silicon layer and BOX layer to the isolated silicon region for connecting the independently voltage controlled isolated silicon region to a voltage. | 12-12-2013 |
20130341720 | IMPLEMENTING GATE WITHIN A GATE UTILIZING REPLACEMENT METAL GATE PROCESS - A method and circuit for implementing field effect transistors (FETs) having a gate within a gate utilizing a replacement metal gate process (RMGP), and a design structure on which the subject circuit resides are provided. A field effect transistor utilizing a RMGP includes a sacrificial gate in a generally central metal gate region on a dielectric layer on a substrate, a source and drain formed in the substrate, a pair of dielectric spacers, a first metal gate and a second metal gate replacing the sacrificial gate inside the central metal gate region, and a second gate dielectric layer separating the first metal gate and the second metal gate. A respective electrical contact is formed on opposite sides of the central metal gate region for respectively electrically connecting the first metal gate and the second metal gate to a respective voltage. | 12-26-2013 |
20140124943 | INTEGRATED DECOUPLING CAPACITOR UTILIZING THROUGH-SILICON VIA - A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region. | 05-08-2014 |
20140127875 | INTEGRATED DECOUPLING CAPACITOR UTILIZING THROUGH-SILICON VIA - A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region. | 05-08-2014 |
20140151896 | IMPLEMENTING ENHANCED POWER SUPPLY DISTRIBUTION AND DECOUPLING UTILIZING TSV EXCLUSION ZONE - Methods and structures implement enhanced power supply distribution and decoupling utilizing Through-Silicon-Via (TSV) exclusion zone areas for contacting one or more metal wiring layers on a semiconductor chip. A first wiring level in the TSV exclusion zone area includes a first wiring shape having a first hole of a first diameter. A dielectric includes second hole of a second diameter larger than the first diameter is provided above the first wiring level concentric with the first hole. A via hole extends through the first and second holes and an etch is performed to expose a top surface portion of the first wiring shape. A thin oxide is grown over the entire bore of the hole; an anisotropic etch is provided to remove horizontal portions of the thin oxide, exposing wiring shapes. The via hole is filled with a selected material to make TSV electrical connection to the exposed wiring shape. | 06-05-2014 |
20140183603 | SIGNAL PATH AND METHOD OF MANUFACTURING A MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE - A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers with signal tracks. The signal tracks have a quality characteristic. The semiconductor device also includes repeater banks to repower signals. The method of manufacture includes defining portions of layers with photomasks having signal track patterns, determining a quality characteristic of the signal track patterns, and selecting a photomask for etching vias. | 07-03-2014 |
20140183640 | GATELESS FINFET - A finFET includes a semiconductor fin formed on a base. The fin further includes a body area between a first vertical surface and a second vertical surface. The finFET includes a first contact adjacent to the first vertical surface of the body area. The first vertical surface is spaced away from the first contact by a first dielectric thickness. Also included is a second contact adjacent to the second vertical surface of the body area. The second vertical surface is spaced away from the second contact by a second dielectric thickness. The first dielectric thickness and second dielectric thickness are configured to allow the first contact and second contact to modulate the body area of the fin. | 07-03-2014 |
20140183659 | SIGNAL PATH AND METHOD OF MANUFACTURING A MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE - A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers with signal tracks. The signal tracks have a quality characteristic. The semiconductor device also includes repeater banks to repower signals. The method of manufacture includes defining portions of layers with photomasks having signal track patterns, determining a quality characteristic of the signal track patterns, and selecting a photomask for etching vias. | 07-03-2014 |
20140184320 | SIGNAL PATH OF A MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE - A multiple-patterned semiconductor device is provided. The semiconductor device includes one or more layers with signal tracks defined by masks and a structure for transferring a signal between signal tracks and repowering the signal. | 07-03-2014 |
20140184321 | SIGNAL PATH OF A MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE - A multiple-patterned semiconductor device is provided. The semiconductor device includes one or more layers with signal tracks defined by masks and a structure for transferring a signal between signal tracks and repowering the signal. | 07-03-2014 |
20140189615 | SIGNAL PATH AND METHOD OF MANUFACTURING A MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE - A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers with signal tracks. The signal tracks have a quality characteristic. The semiconductor device also includes repeater banks to repower signals. The method of manufacture includes defining portions of layers with photomasks having signal track patterns, determining a quality characteristic of the signal track patterns, and selecting a photomask for etching vias. | 07-03-2014 |
20140210051 | METHOD FOR IMPLEMENTING DEEP TRENCH ENABLED HIGH CURRENT CAPABLE BIPOLAR TRANSISTOR FOR CURRENT SWITCHING AND OUTPUT DRIVER APPLICATIONS - A method and structures are provided for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications. A deep oxygen implant is provided in a selected region of substrate. A first deep trench and second deep trench are formed above the deep oxygen implant. The first deep trench is a generally large rectangular box deep trench of minimum width and the second deep trench is a second small area deep trench centered within the first rectangular box deep trench. Ion implantation at relatively high ion pressure and annealing is utilized to form highly doped N+ regions or P+ regions both inside and outside the outside the first deep trench and around the outside the second deep trench region. These regions provide the collector and emitter respectively, and the existing substrate region provides the base region between the collector and emitter regions. | 07-31-2014 |
20140264332 | SEMICONDUCTOR CHIP WITH POWER GATING THROUGH SILICON VIAS - A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground. | 09-18-2014 |
20140264889 | SEMICONDUCTOR DEVICE CHANNELS - A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include at least two channels having a substantially equivalent cross-sectional area. Conductors in separate channels may have different cross-sectional areas. A spacer dielectric on a side of a channel may be included. The method of manufacture includes establishing a signal conductor layer including a first channel and a second channel having a substantially equivalent cross-sectional area, introducing a spacer dielectric on a side of the second channel, introducing a first conductor in the first channel having a first cross-sectional area, and introducing a second conductor in the second channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area. | 09-18-2014 |
20140264942 | SEMICONDUCTOR DEVICE CHANNELS - A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include a signal channel and a power channel. The power channel may include power channel cross-sectional portions. A first conductor in the power channel may have a first cross-sectional area. A second conductor in the signal channel may have a second cross-sectional area. The second cross-sectional area may be smaller than the first cross-sectional area. The method of manufacture includes establishing a signal conductor layer including a signal channel and a power channel, introducing a first conductor in the power channel having a first cross-sectional area, and introducing a second conductor in the signal channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area. | 09-18-2014 |
20140264943 | MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE CHANNELS - A semiconductor device and method of manufacture are provided. The semiconductor device may include a multiple-patterned layer which may include multiple channels defined by multiple masks. A width of a first channel may be smaller than a width of a second channel. A conductor in the first channel may have a conductor width substantially equivalent to a conductor width of a conductor in the second channel. A spacer dielectric on a channel side may be included. The method of manufacture includes establishing a signal conductor layer including channels defined masks where a first channel may have a first width smaller than a second width of a second channel, introducing a spacer dielectric on a channel side, introducing a first conductor in the first channel having a first conductor width, and introducing a second conductor in the second channel having a second conductor width substantially equivalent to the first conductor width. | 09-18-2014 |
20140273439 | SEMICONDUCTOR DEVICE CHANNELS - A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include at least two channels having a substantially equivalent cross-sectional area. Conductors in separate channels may have different cross-sectional areas. A spacer dielectric on a side of a channel may be included. The method of manufacture includes establishing a signal conductor layer including a first channel and a second channel having a substantially equivalent cross-sectional area, introducing a spacer dielectric on a side of the second channel, introducing a first conductor in the first channel having a first cross-sectional area, and introducing a second conductor in the second channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area. | 09-18-2014 |
20140273440 | SEMICONDUCTOR DEVICE CHANNELS - A semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers having channels adapted to carry signals or deliver power. The semiconductor device may include a signal channel and a power channel. The power channel may include power channel cross-sectional portions. A first conductor in the power channel may have a first cross-sectional area. A second conductor in the signal channel may have a second cross-sectional area. The second cross-sectional area may be smaller than the first cross-sectional area. The method of manufacture includes establishing a signal conductor layer including a signal channel and a power channel, introducing a first conductor in the power channel having a first cross-sectional area, and introducing a second conductor in the signal channel having a second cross-sectional area where the second cross-sectional area is smaller than the first cross-sectional area. | 09-18-2014 |
20140273444 | MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE CHANNELS - A semiconductor device and method of manufacture are provided. The semiconductor device may include a multiple-patterned layer which may include multiple channels defined by multiple masks. A width of a first channel may be smaller than a width of a second channel. A conductor in the first channel may have a conductor width substantially equivalent to a conductor width of a conductor in the second channel. A spacer dielectric on a channel side may be included. The method of manufacture includes establishing a signal conductor layer including channels defined masks where a first channel may have a first width smaller than a second width of a second channel, introducing a spacer dielectric on a channel side, introducing a first conductor in the first channel having a first conductor width, and introducing a second conductor in the second channel having a second conductor width substantially equivalent to the first conductor width. | 09-18-2014 |
20140362635 | CAPACITOR BACKUP FOR SRAM - Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state. The method may also include backing up the data written to the SRAM cell by electrically coupling the input node to the capacitive backup circuit. The method may also include restoring the data stored in the capacitive backup circuit to the SRAM cell by electrically coupling the capacitive backup circuit to the input node. | 12-11-2014 |
20140362636 | CAPACITOR BACKUP FOR SRAM - Embodiments of the disclosure provide a method for backing up data in an SRAM device, and an SRAM device that includes a capacitive backup circuit for backing up data in an SRAM device. The method may include writing data to the SRAM cell by applying an input voltage to set an input node of cross-coupled inverters to a memory state. The method may also include backing up the data written to the SRAM cell by electrically coupling the input node to the capacitive backup circuit. The method may also include restoring the data stored in the capacitive backup circuit to the SRAM cell by electrically coupling the capacitive backup circuit to the input node. | 12-11-2014 |
20150076615 | INTERDIGITATED FINFETS - A semiconductor device includes a first fin rising out of a semiconductor base. It further includes a second fin rising out of the semiconductor base. The second fin is substantially parallel to the first fin that forms a span between the first fin and the second fin. A first dielectric layer is deposited on exposed surfaces of a first gate body area of the first fin, a second gate body area of the second fin, and an adjacent surface of the semiconductor base that defines the span between the first and second gate body areas. A gate electrode layer is sandwiched between the first dielectric layer and a second dielectric layer. The semiconductor device includes a third fin interdigitated between the first fin and the second fin within the span. Exposed surfaces of the gate body area of the third fin are in contact with the second dielectric layer. | 03-19-2015 |