Patent application number | Description | Published |
20100264427 | Bipolar Junction Transistor Guard Ring Structures and Method of Fabricating Thereof - Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer. | 10-21-2010 |
20110024768 | SiC AVALANCHE PHOTODIODE WITH IMPROVED EDGE TERMINATION - An avalanche photodiode semiconductor device ( | 02-03-2011 |
20110121883 | SYSTEM AND METHOD FOR PROVIDING SYMMETRIC, EFFICIENT BI-DIRECTIONAL POWER FLOW AND POWER CONDITIONING - A system and method for providing symmetric, efficient bi-directional power flow and power conditioning for high-voltage applications. Embodiments include a first vertical-channel junction gate field-effect transistor (VJFET), a second VJFET, a gate drive coupled to the first VJFET gate and the second VJFET gate. Both VJFETs include a gate, drain (D | 05-26-2011 |
20120104416 | BIPOLAR JUNCTION TRANSISTOR GUARD RING STRUCTURES AND METHOD OF FABRICATING THEREOF - Semiconductor devices with multiple floating guard ring edge termination structures and methods of fabricating same are disclosed. A method for fabricating guard rings in a semiconductor device that includes forming a mesa structure on a semiconductor layer stack, the semiconductor stack including two or more layers of semiconductor materials including a first layer and a second layer, said second layer being on top of said first layer, forming trenches for guard rings in the first layer outside a periphery of said mesa, and forming guard rings in the trenches. The top surfaces of said guard rings have a lower elevation than a top surface of said first layer. | 05-03-2012 |
20120161208 | Semiconductor Devices with Minimized Current Flow Differences and Methods of Same - A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device. | 06-28-2012 |
20140106517 | SEMICONDUCTOR DEVICES WITH MINIMIZED CURRENT FLOW DIFFERENCES AND METHODS OF SAME - A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device. | 04-17-2014 |
20140175460 | SEMICONDUCTOR DEVICES WITH MINIMIZED CURRENT FLOW DIFFERENCES AND METHODS OF SAME - A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device. | 06-26-2014 |
20140268465 | SYSTEM AND METHOD FOR PROVIDING OPTICALLY TRIGGERED CIRCUIT BREAKER - A system/method for providing an optically triggered circuit breaker is provided. The system comprises a junction field-effect transistor (JFET) and gate drive coupled to the JFET's gate. The gate drive applies voltage bias (V | 09-18-2014 |