Patent application number | Description | Published |
20080215792 | Multiple processor system and method including multiple memory hub modules - A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces. | 09-04-2008 |
20080222379 | System and method for memory hub-based expansion bus - A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit. | 09-11-2008 |
20080294856 | MEMORY ARBITRATION SYSTEM AND METHOD HAVING AN ARBITRATION PACKET PROTOCOL - A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub. | 11-27-2008 |
20080294862 | ARBITRATION SYSTEM HAVING A PACKET MEMORY AND METHOD FOR MEMORY RESPONSES IN A HUB-BASED MEMORY SYSTEM - A memory hub module includes a decoder that receives memory requests determines a memory request identifier associated with each memory request. A packet memory receives memory request identifiers and stores the memory request identifiers. A packet tracker receives remote memory responses and associates each remote memory response with a memory request identifier and removes the memory request identifier from the packet memory. A multiplexor receives remote memory responses and local memory responses. The multiplexor selects an output responsive to a control signal. Arbitration control logic is coupled to the multiplexor and the packet memory and develops the control signal to select a memory response for output. | 11-27-2008 |
20080301533 | Dynamic synchronization of data capture on an optical or other high speed communications link - A method and system that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals. | 12-04-2008 |
20090013143 | SYSTEM AND METHOD FOR READ SYNCHRONIZATION OF MEMORY MODULES - A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing. | 01-08-2009 |
20090073647 | APPARATUS AND METHODS FOR A PHYSICAL LAYOUT OF SIMULTANEOUSLY SUB-ACCESSIBLE MEMORY MODULES - A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector. | 03-19-2009 |
20090106591 | SYSTEM AND METHOD FOR ON-BOARD DIAGNOSTICS OF MEMORY MODULES - A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a memory device interface coupled to the memory devices for coupling memory requests to the memory devices. A memory hub diagnostic engine is coupled through a switch to the link interface and the memory device interface to perform diagnostic testing of the memory system. The diagnostic engine includes a maintenance port that provides access to results of the diagnostic testing and through which diagnostic testing commands can be received. | 04-23-2009 |
20090125688 | MEMORY HUB WITH INTERNAL CACHE AND/OR MEMORY ACCESS PREDICTION - A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address. | 05-14-2009 |
20090172480 | System and method for testing a packetized memory device - Integrated circuits, load boards and methods are disclosed, such as those associated with a memory testing system that includes an algorithmic pattern generator generating a pattern of command, address or write data digits according to an algorithm. In one such embodiment, the pattern of digits are applied to a frame generator that arranges the pattern of digits into a packet. The packet is then applied to a plurality of parallel-to-serial converters that convert the packet into a plurality of serial digits of a command/address packet or a write data packet, which are output through a plurality of bit lanes. The system might also include a plurality of serial-to-parallel converters receiving respective sets of digits of a read data packet through respective bit lanes. The read data packet is applied to a frame decomposer that extracts a pattern of read data digits from the packet. An error detecting circuit then determines if any of the received read data digits are erroneous. | 07-02-2009 |
20090282182 | MULTIPLE PROCESSOR SYSTEM AND METHOD INCLUDING MULTIPLE MEMORY HUB MODULES - A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces. | 11-12-2009 |
20090300277 | DEVICES AND METHODS FOR OPERATING A SOLID STATE DRIVE - The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes receiving an indication of a desired number of write input/output operations (IOPs) per unit time performed by the solid state drive. The method can also include managing the number of write IOPs performed by the solid state drive at least partially based on the desired number of write IOPs per unit time, a number of spare blocks in the solid state drive, and a desired operational life for the solid state drive. | 12-03-2009 |
20090300444 | METHOD AND APPARATUS FOR TESTING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES - A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are arranged in a plurality of vaults. The logic circuit die serves as a memory interface device to a memory access device, such as a processor. The logic circuit die includes a plurality of link interfaces and downstream targets for transmitting received data to the vaults. The logic circuit die includes a packet builder and broadcaster configured to receive command, address and data signals over separate interfaces from a conventional tester, format the signals into a packet and broadcast the signals to a plurality of vaults. | 12-03-2009 |
20090327532 | APPARATUS AND METHOD FOR DIRECT MEMORY ACCESS IN A HUB-BASED MEMORY SYSTEM - A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a memory device interface for coupling to the memory devices, the memory device interface coupling memory requests to the memory devices for access to at least one of the memory devices. A switch for selectively coupling the link interface and the memory device interface is further included in the memory hub. Additionally, a direct memory access (DMA) engine is coupled through the switch to the memory device interface to generate memory requests for access to at least one of the memory devices to perform DMA operations. | 12-31-2009 |
20100005217 | MULTI-MODE MEMORY DEVICE AND METHOD - Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice. | 01-07-2010 |
20100005376 | METHOD AND APPARATUS FOR REPAIRING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES - Memory systems, systems and methods are disclosed that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias. | 01-07-2010 |
20100014364 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM - A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time. | 01-21-2010 |
20100036989 | SYSTEM AND METHOD FOR MEMORY HUB-BASED EXPANSION BUS - A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit. | 02-11-2010 |
20100100670 | Out of Order Dram Sequencer - Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus. The memory access requests are executed in the reordered sequence, while the originally received order of the requests is tracked. After execution, data read from the memory device by the execution of the read-type memory access requests are transferred to the respective requestors in the order in which the read requests were originally received. | 04-22-2010 |
20100153794 | SYSTEM AND METHOD FOR ON-BOARD TIMING MARGIN TESTING OF MEMORY MODULES - A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a self-test module. The self-test module includes a pattern generator producing write data having a predetermined pattern, and a flip-flop having a data input receiving the write data. A clock input of the flip-flop receives an internal clock signal from a delay line that receives a variable frequency clock generator. Read data are coupled from the memory devices and their pattern compared to the write data pattern. The delay of the delay line and frequency of the clock signal can be varied to test the speed margins of the memory devices. | 06-17-2010 |
20100191924 | METHOD AND SYSTEM FOR CONTROLLING MEMORY ACCESSES TO MEMORY MODULES HAVING AMEMORY HUB ARCHITECTURE - A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules. | 07-29-2010 |
20110029746 | RECONFIGURABLE MEMORY MODULE AND METHOD - A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes. | 02-03-2011 |
20110075497 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM - A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time. | 03-31-2011 |
20110078496 | STRIPE BASED MEMORY OPERATION - The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed. | 03-31-2011 |
20110082963 | POWER INTERRUPT MANAGEMENT - The present disclosure includes methods for operating a memory system, and memory systems. One such method includes updating transaction log information in a transaction log using write look ahead information; and updating a logical address (LA) table using the transaction log. | 04-07-2011 |
20110113189 | MULTIPLE PROCESSOR SYSTEM AND METHOD INCLUDING MULTIPLE MEMORY HUB MODULES - A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces. | 05-12-2011 |
20110145463 | SYSTEM AND METHOD FOR MEMORY HUB-BASED EXPANSION BUS - A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit. | 06-16-2011 |
20110164446 | APPARATUS AND METHODS FOR A PHYSICAL LAYOUT OF SIMULTANEOUSLY SUB-ACCESSIBLE MEMORY MODULES - A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector. | 07-07-2011 |
20110167238 | METHOD AND SYSTEM FOR CONTROLLING MEMORY ACCESSES TO MEMORY MODULES HAVING A MEMORY HUB ARCHITECTURE - A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules. | 07-07-2011 |
20110219196 | MEMORY HUB WITH INTERNAL CACHE AND/OR MEMORY ACCESS PREDICTION - A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address. | 09-08-2011 |
20110246743 | RECONFIGURABLE MEMORY MODULE AND METHOD - A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes. | 10-06-2011 |
20110271158 | METHOD AND APPARATUS FOR TESTING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES - A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are arranged in a plurality of vaults. The logic circuit die serves as a memory interface device to a memory access device, such as a processor. The logic circuit die includes a plurality of link interfaces and downstream targets for transmitting received data to the vaults. The logic circuit die includes a packet builder and broadcaster configured to receive command, address and data signals over separate interfaces from a conventional tester, format the signals into a packet and broadcast the signals to a plurality of vaults. | 11-03-2011 |
20110296227 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM - A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time. | 12-01-2011 |
20110314199 | APPARATUS AND METHOD FOR DIRECT MEMORY ACCESS IN A HUB-BASED MEMORY SYSTEM - A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a memory device interface for coupling to the memory devices, the memory device interface coupling memory requests to the memory devices for access to at least one of the memory devices. A switch for selectively coupling the link interface and the memory device interface is further included in the memory hub. Additionally, a direct memory access (DMA) engine is coupled through the switch to the memory device interface to generate memory requests for access to at least one of the memory devices to perform DMA operations. | 12-22-2011 |
20120005389 | SYSTEM AND METHOD FOR MEMORY HUB-BASED EXPANSION BUS - A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit. | 01-05-2012 |
20120066461 | MEMORY ARBITRATION SYSTEM AND METHOD HAVING AN ARBITRATION PACKET PROTOCOL - A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub. | 03-15-2012 |
20120089801 | SYSTEM FOR CONTROLLING MEMORY ACCESSES TO MEMORY MODULES HAVING A MEMORY HUB ARCHITECTURE - A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules. | 04-12-2012 |
20120144152 | TRANSACTION LOG RECOVERY - The present disclosure includes methods for transaction log recovery in memory. One such method includes examining a number of entries saved in a transaction log to determine a write pattern, reading the memory based on the write pattern, updating the transaction log with information associated with data read from the memory based on the write pattern, and updating a logical address (LA) table using the transaction log. | 06-07-2012 |
20120226964 | DYNAMIC SYNCHRONIZATION OF DATA CAPTURE ON AN OPTICAL OR OTHER HIGH SPEED COMMUNICATIONS LINK - A method that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals. | 09-06-2012 |
20120239885 | MEMORY HUB WITH INTERNAL CACHE AND/OR MEMORY ACCESS PREDICTION - A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address. | 09-20-2012 |
20120278524 | RECONFIGURABLE MEMORY MODULE AND METHOD - A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes. | 11-01-2012 |
20120303885 | MULTIPLE PROCESSOR SYSTEM AND METHOD INCLUDING MULTIPLE MEMORY HUB MODULES - A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces. | 11-29-2012 |
20120311193 | APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS - Memory system controllers can include a host bus adapter (HBA) and a serial advanced technology attachment (SA) programming compliant device coupled to the HBA via a function-specific interconnect configured to simultaneously transfer a command, a response, and other information between the HBA and the SA programming compliant device. | 12-06-2012 |
20120311197 | APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS - Memory system controllers can include hardware masters, first buffers, and a switch coupled to the hardware masters and to the first buffers. The switch can include second buffers and a buffer allocation management (BAM) circuit. The BAM circuit can include a buffer tag pool. The buffer tag pool can include tags, each identifying a respective first buffer or a respective second buffer. The BAM circuit can be configured to allocate a tag to a hardware master in response to an allocation request from the hardware masters. The BAM circuit can be configured to prioritize allocation of a tag identifying a second buffer over a tag identifying a first buffer. | 12-06-2012 |
20120311388 | APPARATUS AND METHODS FOR PROVIDING DATA INTEGRITY - The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more methods can include, for example: receiving a number of sectors of data to be written to a number of memory devices; appending first metadata corresponding to the number of sectors and including first integrity data to the number of sectors, the first metadata has a particular format; generating second integrity data to be provided in second metadata, the second integrity data corresponding to at least one of the number of sectors (wherein the second metadata has a second format); and generating third integrity data to be provided in the second metadata, the third integrity data including error data corresponding to the second integrity data and the at least one of the number of sectors. | 12-06-2012 |
20120331253 | STRIPE-BASED MEMORY OPERATION - The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed. | 12-27-2012 |
20130010552 | MULTI-MODE MEMORY DEVICE AND METHOD HAVING STACKED MEMORY DICE, A LOGIC DIE AND A COMMAND PROCESSING CIRCUIT AND OPERATING IN DIRECT AND INDIRECT MODES - Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice. | 01-10-2013 |
20130179658 | SYSTEM AND METHOD FOR READ SYNCHRONIZATION OF MEMORY MODULES - A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing. | 07-11-2013 |
20130254627 | STRIPE-BASED MEMORY OPERATION - The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed. | 09-26-2013 |
20130311750 | TRANSACTION LOG RECOVERY - The present disclosure includes methods for transaction log recovery in memory. One such method includes examining a number of entries saved in a transaction log to determine a write pattern, reading the memory based on the write pattern, updating the transaction log with information associated with data read from the memory based on the write pattern, and updating a logical address (LA) table using the transaction log. | 11-21-2013 |
20130326132 | MEMORY SYSTEM AND METHOD HAVING UNIDIRECTIONAL DATA BUSES - A memory system and method includes a unidirectional downstream bus coupling write data from a memory controller to several memory devices, and a unidirectional upstream bus coupling read data from the memory devices to the memory controller. The memory devices each include a write buffer for storing the write data until the respective memory device is no longer busy processing read memory requests. The downstream bus may also be used for coupling memory commands and/or row and column addresses from the memory controller to the memory devices. | 12-05-2013 |
20130326164 | BUFFER CONTROL SYSTEM AND METHOD FOR A MEMORY SYSTEM HAVING OUTSTANDING READ AND WRITE REQUEST BUFFERS - A memory controller and method for managing the issuance of read and write requests to a system memory is provided. The number of outstanding read requests and write requests issued to the system memory are separately monitored and further issuance of read and write requests to the system memory is separately controlled based on the number of outstanding read and write requests, respectively. For example, the issuance of read and write requests can be managed by halting and resuming the issuance of read and write requests to the system memory to maintain the number of outstanding read requests between first and second read thresholds and to maintain the number of outstanding write requests between first and second write thresholds, respectively. | 12-05-2013 |
20130346722 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM - A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time. | 12-26-2013 |
20140032825 | DEVICES AND METHODS FOR OPERATING A SOLID STATE DRIVE - The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes receiving an indication of a desired number of write input/output operations (IOPs) per unit time performed by the solid state drive. The method can also include managing the number of write IOPs performed by the solid state drive at least partially based on the desired number of write IOPs per unit time, a number of spare blocks in the solid state drive, and a desired operational life for the solid state drive. | 01-30-2014 |
20140032939 | APPARATUS POWER CONTROL - The present disclosure includes apparatuses and methods for apparatus power control. A number of embodiments include determining a power profile for each of a number of commands in a command queue that are ready for execution and selecting a portion of the number of commands in the command queue for execution based on the power profiles of the number of commands to control power consumption in the apparatus. | 01-30-2014 |
20140101490 | APPARATUS AND METHODS FOR PROVIDING DATA INTEGRITY - The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more methods can include, for example: receiving a number of sectors of data to be written to a number of memory devices; appending first metadata corresponding to the number of sectors and including first integrity data to the number of sectors, the first metadata has a particular format; generating second integrity data to be provided in second metadata, the second integrity data corresponding to at least one of the number of sectors (wherein the second metadata has a second format); and generating third integrity data to be provided in the second metadata, the third integrity data including error data corresponding to the second integrity data and the at least one of the number of sectors. | 04-10-2014 |
20140108746 | MEMORY ARBITRATION SYSTEM AND METHOD HAVING AN ARBITRATION PACKET PROTOCOL - A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub. | 04-17-2014 |
20140189163 | APPARATUS INCLUDING MEMORY SYSTEM CONTROLLERS AND RELATED METHODS - Memory system controllers can include a host bus adapter (HBA) and a serial advanced technology attachment (SA) programming compliant device coupled to the HBA via a function-specific interconnect configured to simultaneously transfer a command, a response, and other information between the HBA and the SA programming compliant device. | 07-03-2014 |
20140223116 | METHODS FOR SEQUENCING MEMORY ACCESS REQUESTS - Memory access requests are successively received in a memory request queue of a memory controller. Any conflicts or potential delays between temporally proximate requests that would occur if the memory access requests were to be executed in the received order are detected, and the received order of the memory access requests is rearranged to avoid or minimize the conflicts or delays and to optimize the flow of data to and from the memory data bus. The memory access requests are executed in the reordered sequence, while the originally received order of the requests is tracked. After execution, data read from the memory device by the execution of the read-type memory access requests are transferred to the respective requestors in the order in which the read requests were originally received. | 08-07-2014 |
20140298119 | METHOD AND APPARATUS FOR REPAIRING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES - Memory systems, systems and methods are disclosed that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias. | 10-02-2014 |
20140337570 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM - A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time. | 11-13-2014 |
20140359192 | APPARATUS INCLUDING BUFFER ALLOCATION MANAGEMENT AND RELATED METHODS - Memory system controllers can include hardware masters, first buffers, and a switch coupled to the hardware masters and to the first buffers. The switch can include second buffers and a buffer allocation management (BAM) circuit. The BAM circuit can include a buffer tag pool. The buffer tag pool can include tags, each identifying a respective first buffer or a respective second buffer. The BAM circuit can be configured to allocate a tag to a hardware master in response to an allocation request from the hardware masters. The BAM circuit can be configured to prioritize allocation of a tag identifying a second buffer over a tag identifying a first buffer. | 12-04-2014 |