Patent application number | Description | Published |
20090073021 | CASCADE COMPARATOR AND CONTROL METHOD THEREOF - A cascade comparator and a control method thereof are provided. By applying multi-phase clock signals to a plurality of comparators when the plurality of comparators are cascaded together so that each comparator is regenerated before the preceding comparator is reset, a hold switch does not need to be provided between the comparators. Therefore, it is possible to reduce the size and parasitic components of a circuit, operate the circuit at a high speed, remove a glitch caused by any hold switch, and accordingly improve system linearity. | 03-19-2009 |
20090160490 | REFERENCE VOLTAGE GENERATOR OF ANALOG-TO-DIGITAL CONVERTER - A reference voltage generator, which is used in an analog-to-digital converter, minimizes influence of kickback noise by dividing a full scale reference voltage into a number of reference voltages using a ladder resistor unit, and applying the number of reference voltages to a number of comparators, and matches a reference common mode voltage to an input common mode voltage by forming a common feedback loop using another ladder resistor unit which is a replica of the ladder resistor unit. Therefore, since kickback noise is locally discharged by a decoupling capacitor connected to each ladder resistor and a peak value of the kickback noise is also reduced, it is possible to optimize the ladder resistor unit according to power consumption. Also, since the common feedback loop is formed as a replica of the ladder resistor unit, it is possible to match a reference common mode signal to an input common mode signal. | 06-25-2009 |
20090195433 | MULTISTAGE AMPLIFIER AND A METHOD OF SETTLING THE MULTISTAGE AMPLIFIER - A method of settling an amplifier and a multistage amplifier are provided. To settle an amplifier, a plurality of clock signals are, respectively, applied to preset switches, each of which is placed between amplifiers connected in cascade, to open the preset switches sequentially, thereby settling the amplifiers in order. | 08-06-2009 |
20100316174 | DISCRETE TIME FILTER AND RECEIVER INCLUDING THE SAME - A discrete time filter includes a plurality of sampling cells and a first dummy sampling cell. Each of the sampling cells performs a current mode sampling operation based on current input to an input terminal in response to a corresponding one of a plurality of sampling clock signals and is reset in response to a corresponding one of the plurality of sampling clock signals and a first dummy sampling clocks. The first dummy sampling cell alternately performs with the first sampling cell the current mode sampling operation based on current input to the input terminal in response to the first dummy sampling clock signal and is alternately reset with the first sampling cell in response to the first sampling clock signal. | 12-16-2010 |
20110018751 | FOLDING ANALOG-TO-DIGITAL CONVERTER - A folding analog-to-digital converter including: a reference voltage generator, a track-and-hold circuit and a first pre-amplification circuit. The reference voltage generator generates a plurality of reference voltages. The track-and-hold circuit generates a sampling control signal having a voltage level lower than or equal to a level of a power supply voltage by maintaining an initial level of a boost capacitor voltage at a level lower than a level of a power supply voltage, and samples and holds an input voltage signal in response to the generated sampling control signal to generate a sampled signal. The first pre-amplification circuit amplifies each of voltage differences between the sampled signal and each of the plurality of reference voltages. | 01-27-2011 |
20120007758 | SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER AND METHOD OF ANALOG TO DIGITAL CONVERSION - An analog to digital converter includes a digital to analog converting circuit, a comparator and a signal processing circuit. The digital to analog converting circuit samples and holds an analog input signal, and converts digital output data to an analog signal to generate a hold voltage signal. The comparator compares the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data. | 01-12-2012 |
20120081243 | DIGITAL-TO-ANALOG CONVERTER, ANALOG-TO-DIGITAL CONVERTER INCLUDING SAME, AND SEMICONDUCTOR DEVICE - Provided are a capacitor digital-to-analog (DAC), an analog-to-digital converter (ADC) including the capacitor DAC, and a semiconductor device. The DAC includes at least one dummy capacitor configured to cause capacitors included in a capacitor array to have a capacitance that is an integer multiple of the capacitance of a unit capacitor. | 04-05-2012 |
20130335245 | SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER AND METHOD OF ANALOG TO DIGITAL CONVERSION - An analog to digital converter includes a digital to analog converting circuit, a comparator and a signal processing circuit. The digital to analog converting circuit samples and holds an analog input signal, and converts digital output data to an analog signal to generate a hold voltage signal. The comparator compares the hold voltage signal with a reference voltage signal in response to a rising edge and a falling edge of a clock signal to generate a comparison output voltage signal. The signal processing circuit performs successive approximation based on the comparison output voltage signal to generate the digital output data. | 12-19-2013 |
20150042859 | 20987 - A method of operating an image sensor includes generating a plurality of ramping up/down signals, and comparing a correlated double sampled pixel signal produced from an output of a pixel with a correlated double sampled first ramping up/down signal among the plurality of ramping up/down signals in a reset interval. The method further includes comparing the correlated double sampled pixel signal with the correlated double sampled first ramping up/down signal at one sampling time or more in an image interval, and a step of outputting a selected ramping up/down signal among the plurality of ramping up/down signals based on a result of the comparison. | 02-12-2015 |