Kazda
Cara R. Kazda, Stoughton, WI US
Patent application number | Description | Published |
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20130199143 | Panel Filter with Reduced Restriction - A filter assembly, panel filter element, and servicing method is provided for reducing inlet flow restriction from a housing inlet into an inlet plenum and reducing outlet flow restriction from an outlet plenum to a housing outlet. | 08-08-2013 |
Michael A. Kazda, Poughkeepsie, NY US
Patent application number | Description | Published |
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20080209376 | SYSTEM AND METHOD FOR SIGN-OFF TIMING CLOSURE OF A VLSI CHIP - A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes. | 08-28-2008 |
20150040095 | Method of Improving Timing Critical Cells For Physical Design In The Presence Of Local Placement Congestion - Optimizing circuits having a congested placement with a timing critical placement map includes identifying critical circuit components in the placement map and determining failing circuit components in the placement map; determining “non-critical” circuit components safe to be moved; removing selected non critical from the placement map; and optimizing the critical circuit components in a new partial placement image of said map; and reinserting the “non-critical” circuit components back into said placement image. The optimization is performed by circuit transformation operating in congested regions of the placement image enabling cell insertion and modifications that increase cell size. | 02-05-2015 |
Michael Anthony Kazda, Poughkeepsie, NY US
Patent application number | Description | Published |
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20130326458 | TIMING REFINEMENT RE-ROUTING - A design tool can automatically improve timing of nets of a fully routed physical design solution. Nets of a netlist are evaluated against a plurality of re-routing criteria to identify the nets that satisfy at least one of the plurality of re-routing criteria. For each of the nets that satisfy at least one of the plurality of re-routing criteria: several operations are performed. The net is globally re-routed to determine a new global route for the net. Those of the nets that are within a given distance of the new global route are identified. The net is detail re-routed in accordance with the new global route without regard to those of the nets within the given distance of the new global route. Those of the nets within the given distance of the new global route are re-routed after completion of the detailed re-routing of the net. | 12-05-2013 |