Patent application number | Description | Published |
20100305168 | PERSONAL-CARE COMPOSITION COMPRISING A CATIONIC ACTIVE - In one embodiment, a personal-care composition in the form of an oil-in-water emulsion comprises an anionic pairing agent, a cationic active, and an anionic thickener. In another embodiment, the anionic pairing agent is pre-formed from the neutralization of an acid with a base. In another embodiment, the anionic pairing agent is formed in situ from the neutralization of an acid with a base. In one embodiment, the molar ratio of the base to the acid is at least about 0.70. In another embodiment, the equivalent ratio of the anionic pairing agent to the cationic active is at least about 0.70. The personal-care composition allows for previously unattainable levels of the cationic active to locate within the oil phase of the emulsion. | 12-02-2010 |
20100305169 | PERSONAL-CARE COMPOSITION COMPRISING A CATIONIC ACTIVE - A personal-care composition in the form of an oil-in-water emulsion comprises a water phase, an oil phase, an anionic pairing agent, a cationic active, and an anionic thickener. In one embodiment, the anionic pairing agent is pre-formed from the neutralization of an acid with a base. In another embodiment, the anionic pairing agent is formed in situ from the neutralization of an acid with a base. At least 25% by weight of the cationic active is present in the oil phase. In certain embodiments, a method for regulating keratinous tissue condition and a method for improving deliverability of a cationic active in the presence of an anionic thickener comprise the steps of: providing the aforementioned personal-care composition, and applying the composition to keratinous tissue in need of treatment. The personal-care composition allows for previously unattainable levels of the cationic active to locate within the oil phase of the emulsion. | 12-02-2010 |
Patent application number | Description | Published |
20150277914 | LOCK ELISION WITH BINARY TRANSLATION BASED PROCESSORS - Generally, this disclosure provides systems, devices, methods and computer readable media for detection and exploitation of lock elision opportunities with binary translation based processors. The device may include a dynamic binary translation (DBT) module to translate a region of code from a first instruction set architecture (ISA) to translated code in a second ISA and to detect and elide a lock associated with a critical section of the region of code. The device may also include a processor to speculatively execute the translated code in the critical section. The device may further include a transactional support processor to detect a memory access conflict associated with the lock and/or critical section during the speculative execution, roll back the speculative execution in response to the detection, and commit the speculative execution in the absence of the detection. | 10-01-2015 |
20150277915 | Instruction and Logic for Support of Code Modification - A processor includes support for executing binary-translated code including code modifications. The processor includes a processor core that includes a cache to store translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected. The processor core also includes logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor core further includes logic to set a translation indicator in the cache corresponding to the memory location to indicate that it includes translated code to be protected. The processor core also includes logic to request senior store buffer drains of other processor cores of the processor based upon the execution of the translated instruction. | 10-01-2015 |
20150277916 | METHOD AND APPARATUS FOR IMPLEMENTING A DYNAMIC OUT-OF-ORDER PROCESSOR PIPELINE - A hardware/software co-design for an optimized dynamic out-of-order Very Long Instruction Word (VLIW) pipeline. For example, one embodiment of an apparatus comprises: an instruction fetch unit to fetch Very Long Instruction Words (VLIWs) in their program order from memory, each of the VLIWs comprising a plurality of reduced instruction set computing (RISC) instruction syllables grouped into the VLIWs in an order which removes data-flow dependencies and false output dependencies between the syllables; a decode unit to decode the VLIWs in their program order and output the syllables of each decoded VLIW in parallel; and an out-of-order execution engine to execute the syllables preferably in parallel with other syllables, wherein at least some of the syllables are to be executed in a different order than the order in which they are received from the decode unit, the out-of-order execution engine having one or more processing stages which do not check for data-flow dependencies and false output dependencies between the syllables when performing operations. | 10-01-2015 |
20150277975 | Instruction and Logic for a Memory Ordering Buffer - A processor includes an allocator with logic assigning alias hardware resources to instructions within an atomic region of instructions. The atomic region includes reordered instructions. The processor also includes a dispatcher with logic to dispatch instructions from the atomic region of instructions for execution. Furthermore, the processor includes a memory execution unit with logic to populate the memory execution unit with the instructions from the atomic region of instructions including reordered instructions, receive snoop requests and determine whether the snoop request matches memory address data of elements within the memory execution unit, and prevent reassignment of alias hardware resources for any load instructions that are eligible to match the snoop requests. | 10-01-2015 |
20150278025 | CHECKPOINTS ASSOCIATED WITH AN OUT OF ORDER ARCHITECTURE - A checkpoint technique associated with an out of order based architecture of a processing device is described. An instruction may be received by its retirement unit and an identification as to whether the instruction is associated with a speculative error is performed. If the instruction is associated with the speculative error, then a first operation may be performed to replace state values of a first checkpoint of the processing device with state values of a second checkpoint. If the instruction is not associated with the speculative error, then the second checkpoint state may be updated based on the instruction. | 10-01-2015 |
20150278097 | Instruction and Logic for Reducing Data Cache Evictions in an Out-Of-Order Processor - A processor includes a resource scheduler, a dispatcher, and a memory execution unit. The memory execution unit includes logic to identify an executed, unretired store operation in a memory ordered buffer, determine that the store operation is speculative, determine whether an associated cache line in a data cache is non-speculative, and determine whether to block a write of the store operation results to the data cache based upon the determination that the store operation is speculative and a determination that the associated cache line is non-speculative. | 10-01-2015 |
20150301841 | BINARY TRANSLATION REUSE IN A SYSTEM WITH ADDRESS SPACE LAYOUT RANDOMIZATION - Generally, this disclosure provides systems, methods and computer readable media for binary translation (BT) reuse. The system may include a (BT) module to translate a region of code from a first instruction set architecture (ISA) to a second ISA, for execution associated with a first process. The BT module may also be configured to store a first physical page number associated with the translated code and the first process. The system may also include a processor to execute the translated code and to update a virtual address instruction pointer associated with the execution. The system may further include a translation reuse module to validate the translated code for reuse by a second process. The validation may include generating a second physical page number based on a page table mapping of the updated virtual address instruction pointer and matching the second physical page number to the stored first physical page number. | 10-22-2015 |
Patent application number | Description | Published |
20080227829 | Neurogenic compounds - The invention relates to method(s) of use of the compound(s) described herein, e.g. method for stimulating neurogenesis, including in vitro neurogenesis, by contacting neuronal progenitor cells with an effective amount of the compound(s) described herein; method for treatment of a subject in need of treatment with a neurogenic compound; and/or for treatment of a disease or condition associated with damage to the hippocampus. The subject may be a human or a veterinary animal. | 09-18-2008 |
20090203926 | PROCESS FOR SELECTIVELY EXTRACTING PROCYANIDINS - A process is described for selectively extracting cocoa procyanidins from an aqueous mixture of cocoa polyphenols by using a particular sequence of solvents to extract selected procyanidin monomers and/or oligomers. The solvents are n-butyl acetate, ethyl acetate, methyl acetate, diethyl ether, or mixtures of methyl acetate and diethyl ether. Preferably, the aqueous mixture of cocoa polyphenols is first extracted with n-butyl acetate. The mixtures of methyl acetate and diethyl ether are between 25:75 and 75:25 (v/v). | 08-13-2009 |
20100016536 | Process for Analyzing, for Separating, and for Isolating Individual Polar Protic Monomers and/or Oligomers - An improved process for separating and isolating individual polar protic monomer(s) and/or oligomer(s) on the basis of degree of polymerization. A liquid sample containing polar protic monomer(s) and/or oligomer(s) is introduced into a liquid chromatography (LC) column packed with a polar bonded stationary chromatographic phase. The individual polar protic monomer(s) and/or oligomer(s) are separated via a binary mobile phase elution. One or more individual fractions containing the monomer(s) and/or oligomer(s) are eluted. The polar protic monomer(s) and/or oligomer(s) may be proanthocyanidins, hydrolyzable tannins, oligosaccharides, oligonucleotides, peptides, acrylamides, polysorbates, polyketides, poloxarners, polyethylene glycols, polyoxyethylene alcohols or polyvinyl alcohols. The binary mobile phase comprises an A phase consisting essentially of a polar aprotic solvent and a B phase consisting essentially of a polar protic solvent. | 01-21-2010 |
Patent application number | Description | Published |
20080263076 | DYNAMIC GROUP CREATION OR RECONFIGURATION BASED UPON AVAILABLE METADATA - The present invention relates to a method for the dynamic creation or reconfiguration of a contact group listing based upon retrieved metadata. The method comprising identifying a contact that is to be added to a primary contact list, the primary contact list being configured to be accessed by at least one sub-list group, wherein sub-list groups are associated with predetermined metadata classification criteria. The method further comprises interrogating data sources in order to identify metadata that is associated with the contact, and retrieving from the data sources all metadata that has been associated with the contact. The retrieved metadata is subsequently utilized to dynamically generate or reconfigure sub-list groupings in accordance with the information that is retrieved from the metadata. | 10-23-2008 |
20090319725 | Methods, Systems and Computer Program Products for Detection of Frequent Improper Removals of and Changing Writing Policies to Prevent Data Loss in Memory Sticks - Methods, system and computer program products for detection of frequent improper removals of and changing writing policies to prevent data loss in memory sticks. Exemplary embodiments include a method including detecting insertions of the memory stick, detecting removals of the memory stick, tracking a number of times the memory stick has been docked when removed, tracking a number of times the memory stick has been undocked when removed, determining a removal ratio of times the memory has been removed when docked to the number of times the memory stick has been removed when undocked, comparing the removal ratio to a predetermined threshold, caching writes and directory updates, and committing the writes and directory updates to the memory stick when the removal ratio is below the predetermined threshold and, flushing all writes and updates to the memory stick when in the removal ratio is equal to or above the predetermined threshold. | 12-24-2009 |