Patent application number | Description | Published |
20120103609 | COMPOSITIONS AND METHODS FOR WELL COMPLETIONS - Cement retarders for well cements are based on hydrophobins. Hydrophobins are proteins or polypeptides that form hydrophobic coatings on surfaces. The size of the hydrophobins is preferably between about 100 and 350 amino acids, and the preferred hydrophobin concentration is between about 0.001% and 1.0% by weight of cement. Portland cement is the preferred well cement. Cement slurries containing hydrophobins are useful for both primary and remedial cementing applications. | 05-03-2012 |
20120175118 | COMPOSITIONS AND METHODS FOR WELL COMPLETIONS - Expansive cements for use in cementing subterranean wells contain an encapsulated gas-generating substance. The gas-generating substance comprises one or more materials that release hydrogen, nitrogen or both. The gas-generating substance is encapsulated by a coating comprising a polymer. The coating prevents premature gas release at the surface during slurry mixing, and promotes gas release at a desired location in the subterranean well. The released gas may also control the internal pore pressure of the cement slurry, thereby inhibiting the invasion of formation fluids into the borehole. | 07-12-2012 |
20140190128 | Methods for Improving the Flowability of Asphalt Particles - The flowability of asphalt particles may be improved by mixing the particles with comprises further compound comprises Portland cement, calcium aluminate cement, fly ash, blast furnace slag, lime/silica blends, silica, ground limestone, cement kiln dust, chemically bonded phosphate ceramics, zeolites, geopolymers, cellulose, starch, calcium carbonate, colloidal silica, aluminosilicates, and combinations thereof. Treating the asphalt particles with at least one of these compounds inhibits caking during storage and enhances transportability. | 07-10-2014 |
Patent application number | Description | Published |
20080307273 | System And Method For Predictive Failure Detection - A method of predicting failure of an information handling device, such as a server, by monitoring an error rate, i.e., n errors per error period. Errors are reported only if the error rate is exceeded. An error count is kept, and errors are leaked from the count if the time difference between errors is more than the error period. | 12-11-2008 |
20090049257 | System and Method for Implementing a Memory Defect Map - In accordance with the present disclosure, a system and method are herein disclosed for managing memory defects in an information handling system. In an information handling system, a first quantity of memory, such as RAM, may contain defective memory elements. A second quantity of memory is physically coupled to the first quantity of memory and is used to store a memory defect map containing information regarding the location of defective memory elements in the first quantity of memory. The memory defect map may then be referenced by the BIOS or the operating system to preclude use of regions of memory containing defective memory elements. | 02-19-2009 |
20090070760 | Virtual Machine (VM) Migration Between Processor Architectures - A system and method for performing a VM migration which manages a cluster of machines in a pool for live migration to the same feature set or behavior. In certain embodiments, machines within the pool can be configured to emulate a certain feature set to enable a VM migration amongst the similar pools. The emulation can be by either masking reporting of a feature set or enabling/disabling a feature set. The handling of emulation registers within the hardware occurs at a firmware level rather than an operating system or hypervisor level. | 03-12-2009 |
20090103444 | Method and Apparatus for Power Throttling of Highspeed Multi-Lane Serial Links - A method for managing the power consumption of an information handling system including a multi-lane serial link having a lane setting that identifies the number of active lanes in the multi-lane serial link. The method may include determining a number of lanes required for the multi-lane serial link based on one or more I/O devices connected to the information handling system, triggering a reduction of the lane setting of the multi-lane serial link if the lane setting of the multi-lane serial link is greater than the determined number of lanes required, and automatically reducing power to the multi-lane serial link in response to the reduction of the lane setting. | 04-23-2009 |
20090119495 | Architectural Enhancements to CPU Microde Load Mechanism for Information Handling Systems - A method for loading microcode to a plurality of cores within a processor. The method includes loading the microcode to a first core of the plurality of cores within the processor system and generating a broadcast inter process interrupt (IPI) message via the first core. The IPI message causes other cores within the processor system to synchronize respective microcode with the microcode that is loaded into the first core. The synchronizing loads microcode to the plurality of cores without requiring independent loads of microcode to each core. | 05-07-2009 |
20090307698 | INFORMATION HANDLING SYSTEM POWER MANAGEMENT DEVICE AND METHODS THEREOF - An information handling system includes a set of power and performance profiles. Based on which of the profiles has been selected, the information handling system selects a thread scheduling table for provision to an operating system. The thread scheduling table determines the sequence of processor cores at which program threads are scheduled for execution. In a power-savings mode, the corresponding thread scheduling table provides for threads to be concentrated at subset of available processor cores, increasing the frequency with which the information handling system can place unused processors in a reduced power state. | 12-10-2009 |
20100191936 | Method and system for operating-system-independent power management using performance verifications - Systems and methods are disclosed for power management in information handling systems using processor performance data to validate changes to processor performance states. Processor utilization data and processor performance data is obtained during system operation. The processor utilization data is analyzed to determine a desired performance state for the processor. Before setting the actual performance state of the processor to this desired performance state, however, processor performance data is analyzed to determine if prior changes to the performance state have been effective. The performance state of the processor is then changed are maintained based upon this additional performance verification analysis. | 07-29-2010 |
20130185564 | SYSTEMS AND METHODS FOR MULTI-LAYERED AUTHENTICATION/VERIFICATION OF TRUSTED PLATFORM UPDATES - In accordance with the present disclosure, a system and method for multilayered authentication of trusted platform updates is described. The method may include storing first cryptographic data in a personality module of an information handling system, with the first cryptographic data corresponding to a verified firmware component. A second cryptographic data may also be determined, with the second cryptographic data corresponding to an unverified firmware component. The unverified firmware component may be stored in a memory element of the information handling system, and the second cryptographic data may be determined using a processor of the information handling system. The method may further include determining if the first cryptographic data matches the second cryptographic data and updating firmware in the information handling system with the unverified firmware component if the first cryptographic data matches the second cryptographic data, and the unverified firmware component includes a digital signature of a manufacturer. | 07-18-2013 |
20140040646 | METHOD AND APPARATUS FOR POWER THROTTLING OF HIGHSPEED MULTI-LANE SERIAL LINKS - A method for managing the power consumption of an information handling system including a multi-lane serial link having a lane setting that identifies the number of active lanes in the multi-lane serial link. The method may include determining a number of lanes required for the multi-lane serial link based on one or more I/O devices connected to the information handling system, triggering a reduction of the lane setting of the multi-lane serial link if the lane setting of the multi-lane serial link is greater than the determined number of lanes required, and automatically reducing power to the multi-lane serial link in response to the reduction of the lane setting. | 02-06-2014 |
Patent application number | Description | Published |
20080294829 | Method And System Of Supporting Multi-Plugging In X8 And X16 PCI Express Slots - A card having a first device and a second device is plugged into a root port having a predefined root port width. The first device is trained and the device lane width is determined. If the root port width is greater than the device lane width then the root port is dynamically configured via hardware strapping to include a predefined number of adjacent ports with each port having a lane width equal to the device lane width. The root port is reset to force training of the first device and the second device. | 11-27-2008 |
20090240903 | Methods and Apparatus for Translating a System Address - A method for translating a system address includes providing a first system address to a firmware and retrieving a first translation data corresponding to a memory configuration from storage. The first system address is translated into a first physical location utilizing the first translation data, and the first physical location is outputted. | 09-24-2009 |
20090319836 | System And Method For Recovery From Uncorrectable Bus Errors In A Teamed NIC Configuration - A method for recovery from uncorrectable errors in an information handling system including an operating system (OS) and one or more network interface cards (NICS) is provided. The method may include detecting an uncorrectable error; determining whether the uncorrectable error is isolated to a particular NIC; determining whether the particular NIC is teamed with one or more other NICs; and notifying the OS of a successful recovery from the uncorrectable error if it is determined that (a) the uncorrectable error is isolated to a particular NIC, and (b) the particular NIC is teamed with one or more other NICs. | 12-24-2009 |
20100306768 | Methods for Managing Performance States in an Information Handling System - An information handling system (IHS) is disclosed wherein the system includes a processor associated with at least one performance state (P-state), and a memory in communication with the processor. The memory is operable to store a virtualization software and a basic input/out system (BIOS). The BIOS is configured to report a parameter of the P-state to the virtualization software. In addition, the BIOS is configured to transition the processor into a desired P-state. A method for managing performance states in an information handling system (IHS) is further disclosed wherein the method includes providing a basic input/output system (BIOS) in communication with a processor, the processor associated with an at least one performance state (P-state) and reporting a parameter of the at least one P-state to a virtualization software via the BIOS. The method further includes transitioning the processor to a desired P-state via the BIOS. | 12-02-2010 |
20110179312 | System and Method for Recovery From Uncorrectable Bus Errors in a Teamed NIC Configuration - A method for recovery from uncorrectable errors in an information handling system including an operating system (OS) and one or more network interface cards (NICs) is provided. The method may include detecting an uncorrectable error; determining whether the uncorrectable error is isolated to a particular NIC; determining whether the particular NIC is teamed with one or more other NICs; and notifying the OS of a successful recovery from the uncorrectable error if it is determined that (a) the uncorrectable error is isolated to a particular NIC, and (b) the particular NIC is teamed with one or more other NICs. | 07-21-2011 |
20110231697 | SYSTEMS AND METHODS FOR IMPROVING RELIABILITY AND AVAILABILITY OF AN INFORMATION HANDLING SYSTEM - In one aspect, a method for improving reliability and availability of an information handling system is disclosed. Operational data associated with an operating margin may be captured. A threshold specified by a pre-defined profile may be identified. The pre-defined profile may be useable in adjusting the operating margin. The captured operational data may be compared to the pre-defined threshold. A parameter specified by the pre-defined profile may be identified. The operation of a component of the information handling system may be modified based, at least in part, on the identified parameter specified by the pre-defined profile. The modification may result in adjusting the operating margin. | 09-22-2011 |
20130007428 | SYSTEM AND METHOD FOR CUSTOMIZED CONFIGURATION OF INFORMATION HANDLING SYSTEMS - In accordance with embodiments of the present disclosure, a method may include determining if personality information associated with an information handling resource of an information handling system is present on a personality module of the information handling system. The method may also include modifying the information handling resource or a second information handling resource to include the personality information in response to determining that the personality information associated with the information handling resource is present in the personality module. The method may further include executing the information handling resource or the second information handling resource as modified with the personality information. | 01-03-2013 |
20130007455 | SYSTEM AND METHOD FOR ESTABLISHING PERPETUAL TRUST AMONG PLATFORM DOMAINS - A method may include generating a first shared secret for a present boot session of the information handling system and determining if a second shared secret existed for a prior boot session of the information handling system. If the second shared secret existed for the prior boot session, the method may include encrypting the first shared secret with the second shared secret and communicating the first shared secret encrypted by the second shared secret from a first information handling resource to a second information handling resource. If the second shared secret did not exist for the prior boot session, the method may include communicating the first shared secret unencrypted from the first information handling resource to the second information handling resource. The method may additionally include securely communicating between the first information handling resource and the second information handling resource using the first shared secret for encryption and decryption. | 01-03-2013 |
20130191879 | METHODS AND SYSTEMS FOR INFORMATION ASSURANCE AND SUPPLY CHAIN SECURITY - In accordance with additional embodiments of the present disclosure, a method may include storing information regarding one or more components of the information handling system to a database, the database stored on a basic input/output system (BIOS) of the information handling system prior to shipment of an information handling system. The method may also include, between the time of shipment of the information handling system to receipt of the information handling system by an intended customer of the information handling system: logging events associated with one or more components of the information handling system, and storing information associated with the events in the database. The method may further include interfacing with an authorized user of the information associated with the events to allow the authorized user to access the information associated with the events. | 07-25-2013 |
20140237262 | SYSTEM AND METHOD FOR ESTABLISHING PERPETUAL TRUST AMONG PLATFORM DOMAINS - A method may include generating a first shared secret for a present boot session of the information handling system and determining if a second shared secret existed for a prior boot session of the information handling system. If the second shared secret existed for the prior boot session, the method may include encrypting the first shared secret with the second shared secret and communicating the first shared secret encrypted by the second shared secret from a first information handling resource to a second information handling resource. If the second shared secret did not exist for the prior boot session, the method may include communicating the first shared secret unencrypted from the first information handling resource to the second information handling resource. The method may additionally include securely communicating between the first information handling resource and the second information handling resource using the first shared secret for encryption and decryption. | 08-21-2014 |
20140358792 | VERIFYING OEM COMPONENTS WITHIN AN INFORMATION HANDLING SYSTEM USING ORIGINAL EQUIPMENT MANUFACTURER (OEM) IDENTIFIER - A method validates whether a component/device installed within an information handling system (IHS) is an OEM (original equipment manufacturer) programmed device, by: reading identification (ID) data and an identifier code from the target device; generating a unique encrypted sequence using the ID data; providing a unique validation check code based on the ID data; generating a component validation code corresponding to the target device via a decryption process involving the unique encrypted sequence; and comparing the component validation code to the validation check code. The method further includes: in response to the component validation code matching the validation check code, identifying the target device as an OEM programmed device with a valid identifier code stored as the identifier code; and enabling certain processes reserved for only verified OEM programmed devices. The decryption process reverses an encryption process utilized when generating the unique OEM identifier code of the target device. | 12-04-2014 |
20140359303 | Secure Original Equipment Manufacturer (OEM) Identifier for OEM Devices - An authorized information handling system (IHS) generates unique identifier codes for an OEM (programmable) device designed as a component for an IHS. An identifier generation and validation (IGV) controller in the authorized IHS generates a unique encrypted sequence by encrypting identification (ID) data read from the OEM device. The IGV controller generates a unique OEM identifier code by further encrypting the encrypted sequence using a first OEM proprietary code. The IGV controller writes the first identifier code to a pre-specified storage location of the OEM device. According to one embodiment, the IGV controller generates the unique OEM identifier code using a second reversible encryption-decryption component that comprises an Exclusive-OR (XOR) scrambler engine and generates the unique encrypted sequence using a first reversible encryption-decryption component that comprises an LFSR based scrambler, which utilizes polynomial coefficients that are securely generated and maintained. | 12-04-2014 |
20150095631 | SYSTEMS AND METHODS FOR BINDING A REMOVABLE CRYPTOPROCESSOR TO AN INFORMATION HANDLING SYSTEM - In accordance with these and other embodiments of the present disclosure, an information handling system may include a processor and a basic input/output system (BIOS) comprising a program of instructions. The BIOS may be configured to, when read and executed by the processor, calculate a binding secret for binding a cryptoprocessor to a motherboard of the information handling system, the binding secret based on unique identifying information of both the cryptoprocessor and the motherboard, store the binding secret in a non-volatile memory integral to the cryptoprocessor, and validate binding of the cryptoprocessor to the motherboard by comparing a subsequently-calculated binding secret to the binding secret. | 04-02-2015 |
20150363712 | SYSTEMS AND METHODS FOR DISTINGUISHING INFORMATION HANDLING SYSTEM PROVIDER-SUPPORTED INFORMATION HANDLING RESOURCE VIA SYSTEM LICENSE - In accordance with embodiments of the present disclosure, an information handling system comprising a processor, at least one information handling resource communicatively coupled to the processor, and a BIOS comprising a program of instructions executable by the processor and configured to cause the processor to initialize one or more information handling resources of the information handling system. The BIOS may be configured to record information regarding the at least one information handling resource, compare the information to a license for the information handling system to determine if the at least one information handling resource is supported by a provider of the information handling system, and responsive to determining that the information handling system is unsupported by the provider, initiate a remedial action with respect to at least one information handling resource. | 12-17-2015 |
20160098338 | METHODS FOR MANAGING PERFORMANCE STATES IN AN INFORMATION HANDLING SYSTEM - An information handling system (IHS) is disclosed wherein the system includes a processor associated with at least one performance state (P-state), and a memory in communication with the processor. The memory is operable to store a virtualization software and a basic input/out system (BIOS). The BIOS is configured to report a parameter of the P-state to the virtualization software. In addition, the BIOS is configured to transition the processor into a desired P-state. A method for managing performance states in an information handling system (IHS) is further disclosed wherein the method includes providing a basic input/output system (BIOS) in communication with a processor, the processor associated with an at least one performance state (P-state) and reporting a parameter of the at least one P-state to a virtualization software via the BIOS. The method further includes transitioning the processor to a desired P-state via the BIOS. | 04-07-2016 |