Patent application number | Description | Published |
20110267019 | METHODS AND SYSTEMS TO DIGITALLY BALANCE CURRENTS OF A MULTI-PHASE VOLTAGE REGULATOR - Methods and systems to generate a digital error indication of an input signal relative to a reference signal, using resistors, comparators, and latches. The digital error indication may indicate that the input signal is within a range of the reference signal, above the range, or below the range. The methods and systems may be implemented within a multi-phase digital voltage regulator to generate a digital error indication for each of a plurality of phase currents relative to an instantaneous average of the phase currents. The digital voltage regulator may be fabricated on an integrated circuit die with a corresponding load, such as a processor. The digital voltage regulator may include a plurality of multiplier or look-up based gain modules, each to receive a corresponding one of the digital error signals and to output one of three values. Outputs of each gain module may be integrated over time. | 11-03-2011 |
20120154005 | PULSE WIDTH MODULATED SIGNAL GENERATION METHOD AND APPARATUS - Various embodiments associated with methods, apparatuses and systems, digital pulse width modulator (DPWM) comprising a counter logic, including a bitwise negator, and a delay-locked loop (DLL), are disclosed herein. The embodiments may potentially have a shorter processing delay, smaller footprint and/or less power consumption. Other embodiments be also be disclosed or claimed. | 06-21-2012 |
20120159219 | VR POWER MODE INTERFACE - In some embodiments, a control interface and associated control entity are provided to synchronize CPU activities to CPU power delivery network such as VR mode of operation, based on CPU power demands or the prediction of actual CPU current consumption. In some embodiments, the synchronization is controlled in such timely fashion so that the power states or power-related events are entered by a CPU (or core) based on characteristics of a VR supplying power to the CPU (or core). | 06-21-2012 |
20140223205 | MULTIPLE VOLTAGE IDENTIFICATION (VID) POWER ARCHITECTURE, A DIGITAL SYNTHESIZABLE LOW DROPOUT REGULATOR, AND APPARATUS FOR IMPROVING RELIABILITY OF POWER GATES - Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external to the apparatus, the first VID resulting in a first power supply for the first processing core; and generate a second VID different from the first VID, the second VID resulting in a second power supply for the second processing core. Described is an apparatus comprising: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a processing core, and to receive a second power supply as input; an ADC to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative and to generate the digital bus for controlling the plurality of power-gate transistors. | 08-07-2014 |
20140266136 | HYBRID DIGITAL PULSE WIDTH MODULATION (PWM) BASED ON PHASES OF A SYSTEM CLOCK - Pulse width modulation (PWM) based on selectable phases of a system clock may be implemented with respect to leading-edge-modulation (LEM), trailing-edge-modulation (TEM), and/or dual-edge-modulation. An initial pulse may be generated based on a duty command, synchronous with the system clock, and may be registered with a D flip-flop under control of a selected phase of the system clock. Alternatively, a target count may be derived from the duty command, and an edge of the PWM pulse may be initiated when a count of the selected phase equals the target count. The pulse edge may be registered by a D flip-flop to a SR flip-flop under control of the selected phase. The phases of the system clock may be shared amongst multiple systems to generate multiple PWM signals. A system may include a DLL and digital logic, which may consist essentially of combinational logic and registers. | 09-18-2014 |
20150270777 | MASTER-SLAVE DIGITAL VOLTAGE REGULATORS - Described is an apparatus which comprises: a first bridge to be coupled to a first load; a first Pulse Width Modulation (PWM) circuit to drive the first bridge; a second bridge to be coupled to a second load; and a second PWM circuit to drive the second bridge, wherein the first PWM circuit is controlled by a first digital word separate from a second digital word, wherein the second PWM circuit is controlled by the second digital, and wherein the second digital word is derived from the first digital word. | 09-24-2015 |
20150280559 | UNIFIED CONTROL SCHEME FOR NON-INVERTING HIGH-EFFICIENCY BUCK-BOOST POWER CONVERTERS - Methods and apparatus relating to a unified control scheme for non-inverting high-efficiency buck-boost power converters are described. In an embodiment, compensator logic causes a buck-boost power converter to provide an output voltage with a higher voltage level than an input voltage in a boost operational mode of the buck-boost power converter and to provide the output voltage with a lower voltage level than the input voltage in a buck operational mode of the buck-boost power converter. The compensator logic provides N+1 bits to Pulse Width Modulation (PWM) generator logic to cause the buck-boost power converter to provide the output voltage. One of the N+1 bits indicates whether the buck-boost power converter is to provide the buck operation or the boost operation. Other embodiments are also disclosed and claimed. | 10-01-2015 |
20160006350 | TECHNIQUES FOR REDUCING SWITCHING NOISE AND IMPROVING TRANSIENT RESPONSE IN VOLTAGE REGULATORS - Methods and apparatus relating to reducing switching noise and improving transient response in voltage regulators are described. In an embodiment, one or more pulses are inserted into an output waveform of a voltage regulator. The one or more pulses introduce multiple frequencies into the output waveform of the voltage regulator (e.g., to reduce acoustic noise). In another embodiment, the output voltage of a voltage regulator is modified in response to comparison of the output voltage with at least one of a plurality of threshold values. The plurality of threshold values includes an upper trigger point voltage value and a lower trigger point voltage value. Other embodiments are also disclosed and claimed. | 01-07-2016 |
Patent application number | Description | Published |
20090061849 | REDUCING CO-INTERFERENCE ON A MULTI-RADIO PLATFORM - A wireless communications device in a first network with contention-based access may send a special frame to one or more other devices in the first network, informing them that it will not be available to receive any transmissions during a specified time period. The frame may also specify a delay period, indicating when the period of unavailability will start. When the device sending the special frame also has a co-located radio that operates in a second network that uses centrally-controlled scheduling, this special frame may be used to prevent other devices in the first network from sending it any transmissions while the co-located radio is communicating in the second network, thereby reducing the chance of interference between the two co-located radios. | 03-05-2009 |
20100317408 | POWER CONSERVATION FOR MOBILE DEVICE DISPLAYS - Power conservation for mobile device displays. An embodiment of a method includes generating display images for a display screen of a mobile device, and transitioning the mobile device to a reduced power consumption state. The reduced power consumption state includes reducing one or more illumination factors for the display screen; and reducing one or more animation factors for the display screen. | 12-16-2010 |
20100319052 | DYNAMIC CONTENT PREFERENCE AND BEHAVIOR SHARING BETWEEN COMPUTING DEVICES - A remote user persona is received at a computing device. The computing device includes a local user persona having a plurality of subsets relating to preferences of a user of the computing device. The remote user persona is synchronized with the local user persona at the computing device and, accordingly, the behavior of the computing device is adjusted. | 12-16-2010 |
20110222537 | NETWORK CONTROLLER CIRCUITRY TO ISSUE AT LEAST ONE PORTION OF PACKET PAYLOAD TO DEVICE IN MANNER THAT BY-PASSES COMMUNICATION PROTOCOL STACK INVOLVEMENT - An embodiment may include network controller to be comprised in a first node. The node may be communicatively coupled to a network and may include a host processor to execute an operating system environment. The operating system environment may include, at least in part, a communication protocol stack and an application. The circuitry may receive, at least in part, a packet from the network. The packet may include, at least in part, a header and payload. At least one portion of the payload may be associated with the application. The circuitry may issue at least one portion of the header to the stack. The circuitry may issue the at least one portion of the payload to a destination device in a manner that by-passes involvement of the stack. The destination device may be specified, at least in part, by the application. Many alternatives, variations, and modifications are possible. | 09-15-2011 |
20130012319 | MECHANISM FOR FACILITATING HYBRID CONTROL PANELS WITHIN GAMING SYSTEMS - A mechanism is described for facilitating hybrid control panels within gaming systems according to one embodiment of the invention. A method of embodiments of the invention includes employing one or more hybrid control panels at a computing device. The computing device may include a gaming device. The method may further include detecting user movements across a surface of each of the one or more hybrid control panels. The detecting may be performed at least in part using sensors of the hybrid control panels. The method may further include interpreting the user movements, and facilitating actions based on the interpreted user movements. | 01-10-2013 |
20130019263 | MECHANISM FOR FACILITATING MULTIPLE MULTIMEDIA VIEWING PLANES IN MEDIA DISPLAY SYSTEMS - A mechanism is described for facilitating multiple multimedia viewing planes in media display systems according to one embodiment of the invention. A method of embodiments of the invention includes using a plurality of multimedia planes corresponding to a plurality of multimedia content types. The plurality of multimedia planes may be integrated to be presented through an integrated user interface at a media processing device. The method may further include selecting, via the integrated user interface, one or more content categories from a plurality of multimedia content categories, and presenting, via a multimedia plane of the plurality of multimedia planes, contents associated with the one or more selected content categories. | 01-17-2013 |
20130157646 | POWER CONSERVATION FOR MOBILE DEVICE DISPLAYS - Power conservation for mobile device displays. An embodiment of a method includes generating display images for a display screen of a mobile device, and transitioning the mobile device to a reduced power consumption state. The reduced power consumption state includes reducing one or more illumination factors for the display screen; and reducing one or more animation factors for the display screen. | 06-20-2013 |
20130265269 | MOBILE DEVICE REJECTION OF UNINTENTIONAL TOUCH SENSOR CONTACT - Mobile device rejection of unintentional sensor contact. An embodiment of a mobile device includes a first touch sensor to detect contact by a user of the mobile device for input of gestures by the user, a memory to store indicators of unintentional contact to the first touch sensor, and a processor to evaluate contact to the first touch sensor. The processor compares a contact with the first touch sensor to the indicators of unintentional contact to determine if the contact is unintentional, and the mobile device rejects the contact as an input to the mobile device if the contact is determined to be unintentional and accepts the contact as an input to the mobile device if the contact is determined to be intentional. | 10-10-2013 |
20130271419 | TRANSFORMING MOBILE DEVICE SENSOR INTERACTION TO REPRESENT USER INTENT AND PERCEPTION - Transforming mobile device sensor interaction to represent user intent and perception. An embodiment of a mobile device includes a display screen for the display of data and images and a touch sensor to detect a motion of a gesture made by a thumb or other finger of a user of the device. The mobile device further includes a module to transform the motion detected by the touch sensor to generate a modified motion to reflect a perception of the user, where the modified motion is to be applied as an input relating to the display screen. | 10-17-2013 |
20130285969 | DETECTION OF GESTURE DATA SEGMENTATION IN MOBILE DEVICES - Detection of gesture data segmentation in mobile devices. An embodiment of a mobile device includes an edge, the edge including at least a first side, and a first touch sensor of one or more touch sensors, the first touch sensor being a side touch sensor to detect contact with the first side of the mobile device. The mobile device further includes one or more motion detection elements to generate motion data representing motion of the mobile device through space over a period of time, a buffer for the storage of the motion data, and a gesture recognition module to interpret the motion data stored in the buffer, wherein the mobile device begins the storage of the motion data in the buffer upon detection of a start of gesture data event, the start of gesture data event including contact with the first touch sensor. | 10-31-2013 |
20130285982 | MECHANISM FOR INTERPRETING TOUCHES TO A PAD COVER OVER A SENSOR PAD AT A COMPUTING DEVICE - A mechanism is described for interpreting touches to a pad cover placed over a sensor external to a computing device. A method of embodiments of the invention includes sensing a touch on a pad cover covering a capacitive sensor of a computing device. The sensing may include determining a capacitive intensity that corresponds to an amount of pressure applied to the pad cover via the touch. The method may further include interpreting the capacitive intensity as measured by the capacitive sensor across a pad cover gap to determine the amount of pressure applied to the pad cover, determining user intent based on the interpreted capacitive intensity and the determined corresponding amount of applied pressure relating to the touch, and facilitating an action in accordance with the user intent. | 10-31-2013 |
20130293505 | MULTI-DIMENSIONAL INTERACTION INTERFACE FOR MOBILE DEVICES - Method and apparatus for multi-dimensional interaction interface for mobile devices. An embodiment of a mobile device includes a touch screen to provide a display and to generate a touch screen signal upon contact to the touch screen, a touch sensor to generate a touch sensor signal upon contact to the touch sensor, and a module to provide for cooperative operation of the touch screen signal and the touch sensor signal in providing input to the mobile device upon determining that an input to the touch screen indicates a multipoint input. | 11-07-2013 |
20140081572 | PROVISION OF NAVIGATION SERVICE INCLUDING REPORTING OF ELEVATION INFORMATION AND/OR VERTICAL GUIDANCE - Methods, apparatuses and storage medium associated with navigation service are disclosed. In various embodiments, a method may include collecting, by a client mobile device, ambient barometric pressure information at a current location of the client mobile device. The method may further include providing, by the mobile device, contemporaneous navigation assistance to a user of the mobile device or for a user of the mobile device, assisted by a remote navigation assistance service. Assistance by the remote navigation service is associated with determining the current elevation level, based at least in part on ambient barometric pressure information collected by the client mobile device and by one or more crowdsourced mobile devices at the current location. Other embodiments may be disclosed or claimed. | 03-20-2014 |
20140089375 | DETERMINING POINTS OF INTEREST WITHIN A GEOFENCE - Embodiments of apparatus, packages, computer-implemented methods, systems, devices, and computer-readable media are described herein for a mobile computing device with a primary processing unit configured to operate in a normal mode and a reduced power mode. The mobile computing device may include a secondary processing unit, coupled with the primary processing unit, configured to provide, to a remote computing server, location data of the mobile computing device. The secondary processing unit may be configured to receive, from the remote computing server, one or more POIs contained within a geofence, identified based on the provided location data. The providing and receiving may be performed on behalf of the primary processing unit while the primary processing unit is in the reduced power mode. Operation of the secondary power processing unit may require less power than operation of the primary processing unit in the normal mode. | 03-27-2014 |
20140095306 | DIGITAL SIGN ADVERTISEMENT SELECTION BASED ON MOBILE DEVICE ACTIVITY - Various embodiments are directed to cooperation among computing devices to employ visually identifiable traits of a person and data concerning their online activities to determine subjects of interest to them and select advertisements. An apparatus comprises a processor circuit; an interface operative to communicatively couple the processor circuit to a network; and a storage communicatively coupled to the processor circuit and arranged to store a sequence of instructions operative on the processor circuit to: monitor online activities comprising interactions with a computing device via the interface and the network; store collected data about the online activities; store profile data comprising visually identifiable traits; detect a signage device; and form a link with the signage device via the interface and transmit the profile data to the signage device via the link in response to detection of the signage device. Other embodiments are described and claimed herein. | 04-03-2014 |
20140270197 | LOW POWER AUDIO TRIGGER VIA INTERMITTENT SAMPLING - Systems and methods may provide for using an audio front end of a mobile device to sampled audio from an audio signal during a first portion of a periodic detection window, and reducing a power consumption of one or more components of the audio front end during a second portion of the periodic detection window. Additionally, a determination may be made as to whether voice activity is present in the audio signal based at least in part on the sampled audio. In one example, the length of the first portion and the length of the second portion are defined by a duty cycle of the periodic detection window. | 09-18-2014 |
20150091712 | MODIFICATION OF INDICATORS CORRESPONDING TO ALERTS - Various methods and systems for modifying an indicator corresponding to an alert are described herein. One example method includes detecting an alert with a computing device. The method also includes monitoring a noise level in an environment surrounding a computing device. In addition, the method includes modifying the indicator corresponding to the alert based on the noise level. Furthermore, the method includes providing the modified indicator corresponding to the alert. | 04-02-2015 |
20150106715 | MECHANISM FOR FACILITATING MULTIPLE MULTIMEDIA VIEWING PLANES IN MEDIA DISPLAY SYSTEMS - A mechanism is described for facilitating multiple multimedia viewing planes in media display systems according to one embodiment of the invention. A method of embodiments of the invention includes using a plurality of multimedia planes corresponding to a plurality of multimedia content types. The plurality of multimedia planes may be integrated to be presented through an integrated user interface at a media processing device. The method may further include selecting, via the integrated user interface, one or more content categories from a plurality of multimedia content categories, and presenting, via a multimedia plane of the plurality of multimedia planes, contents associated with the one or more selected content categories. | 04-16-2015 |
20150179189 | PERFORMING AUTOMATED VOICE OPERATIONS BASED ON SENSOR DATA REFLECTING SOUND VIBRATION CONDITIONS AND MOTION CONDITIONS - Systems and methods may provide for determining a sound vibration condition of an ambient environment of a wearable device and determining a motion condition of the wearable device. In addition, one or more automated voice operations may be performed based at least in part on the sound vibration condition and the motion condition. In one example, two or more signals corresponding to the sound vibration condition and the motion condition may be combined. | 06-25-2015 |
20150186194 | ELECTRONIC DEVICE TO PROVIDE NOTIFICATION OF EVENT - An electronic device may be provided that includes logic, at least partially implemented in hardware, to detect an occurrence of a blocking instance at the electronic device, and store information related to an event received at the electronic device, the event received during the blocking instance, in response to the occurrence of the blocking instance at the electronic device. | 07-02-2015 |
20150186636 | EXTENDING USER AUTHENTICATION ACROSS A TRUST GROUP OF SMART DEVICES - Particular embodiments described herein provide for a wearable electronic device with a biometric sensor and logic. At least a portion of the logic is implemented in hardware. The logic is configured to receive input data indicative of biometric input and attempt to authenticate the input data based, at least in part, on at least one biometric credential of an authorized user. The logic is configured to establish a wireless connection to a smart device, determine whether the smart device is included in a trust group of one or more smart devices, and send a communication to unlock the smart device when the input data is successfully authenticated and when the trust group includes the smart device. | 07-02-2015 |
20150187206 | TECHNIQUES FOR DETECTING SENSOR INPUTS ON A WEARABLE WIRELESS DEVICE - Various embodiments are generally directed to an apparatus, method and other techniques for detecting, by one or more sensor components, at least one sensor input, and executing, by logic, at least one instruction to cause an event on a wearable wireless device, the event comprising at least one of a change in a physical parameter on the wearable wireless device and a wireless communication with a computing device via a transceiver. | 07-02-2015 |
20150187369 | INTELLIGENT ANCILLARY ELECTRONIC DEVICE - In one example a controller comprises logic, at least partially including hardware logic, configured to detect a key phrase in a received audio signal, and in response to the key phrase, to transmit a signal to a personal assistant in a remote electronic device, determine whether an audio input was received, and in response to a determination that additional audio input was received prior to receiving a response from the personal assistant in the remote electronic device, to buffer the audio input in a memory and forward the audio input to the personal assistant in the remote electronic device. Other examples may be described. | 07-02-2015 |
20150189683 | INTELLIGENT WIRELESS CHARGING DEVICE - In one example a base station for an electronic device comprises a charging station, an audio interface, logic, at least partially including hardware logic, configured to detect a first electronic device within a geographic region proximate the charging device, and in response to detecting the first electronic device | 07-02-2015 |
20150245154 | MECHANISM AND APPARATUS FOR SEAMLESS VOICE WAKE AND SPEAKER VERIFICATION - Technologies are described herein that allow a user to wake up a computing device operating in a low-power state and for the user to be verified by speaking a single wake phrase. Wake phrase recognition is performed by a low-power engine. In some embodiments, the low-power engine may also perform speaker verification. In other embodiments, the mobile device wakes up after a wake phrase is recognized and a component other than the low-power engine performs speaker verification on a portion of the audio input comprising the wake phrase. More than one wake phrases may be associated with a particular user, and separate users may be associated with different wake phrases. Different wake phrases may cause the device transition from a low-power state to various active states. | 08-27-2015 |
20150317687 | SYSTEM AND METHOD FOR ANALYTICS-BASED ADVERTISING - Various systems and methods for analytics-based advertising are described herein. A system for analytics-based advertising comprises a processing module to receive vehicle traffic data; obtain a vehicle identification of a vehicle from the vehicle traffic data, use the vehicle identification to classify the vehicle into a demographic profile, and calculate a demographic model from the demographic profile. The system includes an advertising module to access a group of advertisements and select an advertisement from the group of advertisements based on the demographic model. The system includes a presentation module to cause the advertisement to be displayed on an outdoor advertising apparatus. | 11-05-2015 |
20150379421 | USING A GENERIC CLASSIFIER TO TRAIN A PERSONALIZED CLASSIFIER FOR WEARABLE DEVICES - Systems and methods may provide for using one or more generic classifiers to generate self-training data based on a first plurality of events associated with a device, and training a personal classifier based on the self-training data. Additionally, the one or more generic classifiers and the personal classifier to may be used to generate validation data based on a second plurality of events associated with the device. In one example, the personal classifier is substituted for the one or more generic classifiers if the validation data indicates that the personal classifier satisfies a confidence condition relative to the one or more generic classifiers. | 12-31-2015 |
Patent application number | Description | Published |
20080238736 | BINARY-TO-BCD CONVERSION - Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value. | 10-02-2008 |
20090003589 | Native Composite-Field AES Encryption/Decryption Accelerator Circuit - A system comprises reception of input data of a Galois field GF(2 | 01-01-2009 |
20090168767 | MULTI-CORE PROCESSOR AND METHOD OF COMMUNICATING ACROSS A DIE - A multi-core die is provided that allows packets to be communicated across the die using resources of a packet switched network and a circuit switched network. | 07-02-2009 |
20090172068 | METHOD AND APPARATUS FOR EFFICIENTLY IMPLEMENTING THE ADVANCED ENCRYPTION STANDARD - Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((2 | 07-02-2009 |
20120328097 | APPARATUS AND METHOD FOR SKEIN HASHING - Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data. | 12-27-2012 |
20140013082 | RECONFIGURABLE DEVICE FOR REPOSITIONING DATA WITHIN A DATA WORD - Disclosed is a system and device and related methods for data manipulation, especially for SIMD operations such as permute, shift, and rotate. An apparatus includes a permute section that repositions data on sub-word boundaries and a shift section that repositions the data distances smaller than the sub-word width. The sub-word width is configurable and selectable, and the permute section and shift section may operate on different boundary widths. In a first stage, the permute section repositions the data at the nearest sub-word boundary and, in a second stage, the shift section repositions the data to its final desired position. The shift section includes multi-stages set in a logarithmic cascade relationship. Additionally, each shifter within each of the multi-stages is highly connected, allowing fast and precise data movements. | 01-09-2014 |
20140028677 | GRAPHICS LIGHTING ENGINE INCLUDING LOG AND ANTI-LOG UNITS - Disclosed is an apparatus and method for generating a lighting value based on a number of lighting factors. A lighting accelerator first converts an ambient portion, a diffuse light portion, and a specular light portion of the lighting factors into the log domain. Then, data combination units operate on the lighting factors after they have been converted. Then, the lighting factors are converted back from the log domain using anti-log processing. Converting the lighting factors into the log domain is accomplished by using a series of linear equations using coefficients that are all based on powers of two, and are therefore easily calculable. Further, while in the log domain, the specular light portion of the lighting factor is operated on by a special purpose multiplier that uses a truncated partial product tree, saving area and power with only a negligible amount of error. | 01-30-2014 |
20140201540 | SECURE KEY STORAGE USING PHYSICALLY UNCLONABLE FUNCTIONS - Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor. | 07-17-2014 |
20150086007 | COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT - Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area. | 03-26-2015 |
20150188829 | PRIORITY-BASED ROUTING - Disclosed herein is a router configured for priority-based routing. The router is configured to receive a plurality of packets, wherein each packet is assigned a priority value. The router includes an output circuit configured to select the packet with the highest priority value. The output circuit is configured to forward the priority value of the selected packet to a second router. The output circuit is configured to transfer the selected packet to the second router when the link between the first router and the second router is available. | 07-02-2015 |
Patent application number | Description | Published |
20090003428 | Method and apparatus for treating a signal - A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle. | 01-01-2009 |
20090085637 | Apparatus effecting interface between differing signal levels - An apparatus includes: a signal receiving unit receiving an input signal and presenting a first signal varying within a first signal range; a signal treating unit coupled with the signal receiving unit, receiving the first signal and presenting a second signal varying within a second signal range; and an output unit coupled with the signal treating unit. The signal treating unit and the output unit receive a control signal. The signal treating unit responds to the control signal to provide the second signal to the output unit when the control signal has a first value and to not provide the second signal to the output unit when the control signal has a second value. The output unit permits presentation of an output signal when the control signal has the first value and establishes the output signal at a predetermined value when the control signal has the second value. | 04-02-2009 |
20090167351 | CO-PROCESSOR HAVING CONFIGURABLE LOGIC BLOCKS - A co-processor system is provided that includes an array of configurable logic blocks (CLBs). Each CLB including a plurality of look-up tables and a plurality of adders. Each CLB may be dynamically reconfigurable to perform a plurality of logical functions. | 07-02-2009 |
20090168483 | Ultra low voltage and minimum operating voltage tolerant register file - Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes controlled by complementary write word lines. Other embodiments are also described. | 07-02-2009 |
20090168557 | Ultra wide voltage range register file circuit using programmable triple stacking - Methods and apparatus relating to expanding the operational voltage range of data storage circuits are described. In an embodiment, low voltage data storage circuit operation is improved by driving a transistor with a control word line programmable circuit. Other embodiments are also described. | 07-02-2009 |
20100082718 | COMBINED SET BIT COUNT AND DETECTOR LOGIC - A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word). | 04-01-2010 |
20110158403 | ON-THE-FLY KEY GENERATION FOR ENCRYPTION AND DECRYPTION - Methods and apparatus to provide on-the-fly key computation for Galois Field (also referred to Finite Field) encryption and/or decryption are described. In one embodiment, logic generates a cipher key, in a second cycle, based on a previous cipher key, generated in a first cycle that immediately precedes the second cycle. Other embodiments are also described. | 06-30-2011 |
20120072703 | SPLIT PATH MULTIPLY ACCUMULATE UNIT - In one embodiment, a processor includes a multiply-accumulate (MAC) unit having a first path to handle execution of an instruction if a difference between at least a portion of first and second operands and a third operand is less than a threshold value, and a second path to handle the instruction execution if the difference is greater than the threshold value. Based on the difference, at least part of the third operand is to be provided to a multiplier of the MAC unit or to a compressor of the second path. Other embodiments are described and claimed. | 03-22-2012 |
20130271199 | VOLTAGE LEVEL SHIFT WITH INTERIM-VOLTAGE-CONTROLLED CONTENTION INTERRUPT - Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (VLS) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing. The VLS may include contention circuitry, a contention interrupter, and an interrupt controller to generate a contention-interrupt control having an interim voltage swing. A lower limit of the interim voltage swing may correspond to a lower limit of the output voltage swing. An upper limit of the interim voltage swing may correspond to an upper limit of the input voltage swing. The VLS may be implemented to level shift true and complimentary logical states, such as with cascode voltage switch logic (CVSL). The interim-voltage-controlled contention interrupter may help to maintain voltages within process-based voltage reliability limits of the contention interrupter, with relatively little delay, and relatively little power and area consumption. | 10-17-2013 |
20130339649 | SINGLE INSTRUCTION MULTIPLE DATA (SIMD) RECONFIGURABLE VECTOR REGISTER FILE AND PERMUTATION UNIT - An apparatus may comprise a register file and a permutation unit coupled to the register file. The register file may have a plurality of register banks and an input to receive a selection signal. The selection signal may select one or more unit widths of a register bank as a data element boundary for read or write operations. | 12-19-2013 |
20140105303 | Motion Estimation for Video Processing - In accordance with some embodiments, the complexity of motion estimation algorithms that use Haar, SAD and Hadamard transforms may be reduced. In some embodiments, the number of summations may be reduced compared to existing techniques and some of the existing summations may be replaced with compare operations. In some embodiments, additions are replaced with compares in order to balance delay and area or energy or power considerations. | 04-17-2014 |
20140188968 | VARIABLE PRECISION FLOATING POINT MULTIPLY-ADD CIRCUIT - Embodiments of the present invention may provide methods and circuits for energy efficient floating point multiply and/or add operations. A variable precision floating point circuit may determine the certainty of the result of a multiply-add floating point calculation in parallel with the floating-point calculation. The variable precision floating point circuit may use the certainty of the inputs in combination with information from the computation, such as, binary digits that cancel, normalization shifts, and rounding, to perform a calculation of the certainty of the result. A floating point multiplication circuit may determine whether a lowest portion of a multiplication result could affect the final result and may induce a replay of the multiplication operation when it is determined that the result could affect the final result. | 07-03-2014 |
20140266297 | HARDWARE-EMBEDDED KEY BASED ON RANDOM VARIATIONS OF A STRESS-HARDENED INEGRATED CIRCUIT - An IC cell designed to assert one of multiple possible output states, each with equal probability, implemented to assert a pre-determined one of the multiple output states based on random variations within the IC cell, such as random process variations. An array of IC cells is configurable to provide a hardware-embedded key upon power-up that is unique to the combination of random variations of selected IC cells, resistant to tampering prior to and during manufacture, and tolerant to aging, instantaneous thermal noise, and environmental variations, such as voltage and temperature fluctuations. The key may be used as, without limitation, a Platform Root Key, a High-Bandwidth Digital Content Protection (HDCP) key, an Enhanced Privacy Identification (EPID) key, and/or an Advanced Access Content System (AACS) key. Also disclosed are techniques to measure stability and stress-harden an IC cell based on output states of the IC cell. | 09-18-2014 |
20150023500 | APPARATUS AND METHOD FOR SKEIN HASHING - Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data. | 01-22-2015 |
20150071282 | ARCHITECTURE AND METHOD FOR HYBRID CIRCUIT-SWITCHED AND PACKET-SWITCHED ROUTER - Techniques and mechanisms for performing circuit-switched routing and packet-switched routing for network communication. In an embodiment, a router evaluates control information of a packet received by the router, the evaluation to detect whether the packet includes data for a sideband communication. Based on the evaluation, the router performs a selection from among a plurality of modes of the router, the plurality of modes including a first mode to route the packet for packet-switched communication of sideband data in a network. The plurality of modes also includes a second mode to configure a circuit-switched channel according to the packet. In another embodiment, the router determines a direction for routing a packet in a hierarchical network, wherein the determining of the direction is based on a level of the router in a hierarchy of the hierarchical network. | 03-12-2015 |
20150116019 | APPARATUS AND METHOD FOR LOW POWER FULLY-INTERRUPTIBLE LATCHES AND MASTER-SLAVE FLIP-FLOPS - Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop. | 04-30-2015 |
20150178143 | USING DARK BITS TO REDUCE PHYSICAL UNCLONABLE FUNCTION (PUF) ERROR RATE WITHOUT STORING DARK BITS LOCATION - Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key manager component coupled to the processor core. The secure key manager includes the PUF component, and a dark-bit masking circuit coupled to the PUF component. The dark-bit masking circuit is to measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit. The dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window. The dark-bit masking circuit is to output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit and set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit. | 06-25-2015 |
20150220470 | METHOD, APPARATUS AND SYSTEM FOR A SOURCE-SYNCHRONOUS CIRCUIT-SWITCHED NETWORK ON A CHIP (NOC) - In an embodiment, a router includes multiple input ports and output ports, where the router is of a source-synchronous hybrid network on chip (NoC) to enable communication between routers of the NoC based on transitions in control flow signals communicated between the routers. Other embodiments are described and claimed. | 08-06-2015 |
20150249442 | APPARATUS AND METHOD FOR LOW POWER FULLY-INTERRUPTIBLE LATCHES AND MASTER-SLAVE FLIP-FLOPS - Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop. | 09-03-2015 |
20150381202 | HYBRID CAM ASSISTED DEFLATE DECOMPRESSION ACCELERATOR - Disclosed is an integrated circuit including a memory device including a first portion and a second portion. The first portion is a first type of content addressable memory (CAM) with a first set of cells and the second portion is a second type of CAM with a second set of cells. The first set of cells is smaller than the second set of cells. The integrated circuit further includes a decompression accelerator coupled to the memory device, the decompression accelerator to generate a plurality of length codes. Each of the plurality of length codes include at least one bit. The plurality of length codes are generated using a symbol received from an encoded data stream that includes a plurality of symbols. The decompression accelerator further to store the plurality of length codes in the first portion of the memory device in an order according to their respective number of bits. | 12-31-2015 |