Patent application number | Description | Published |
20090052456 | Packet-processing apparatus and method - The present invention provides a packet-processing apparatus for receiving and processing N packets in a series, wherein N is a natural number, and each of the packets has a current header. Additionally, the packet-processing apparatus includes an agent, a processing unit, a monitoring unit, a lookup table, and a control unit. Particularly, the packet-processing apparatus according to the invention can process the N packets effectively and flexibly. | 02-26-2009 |
20090210577 | DIRECT MEMORY ACCESS SYSTEM AND METHOD USING THE SAME - The invention discloses a DMA system capable of being adapted to various interfaces. The DMA system includes the following advantages: 1) the software porting effort can be reduced when different interfaces are integrated into a SoC; 2) a flexible DMA that could provide protocol transparency and could be ported into different interfaces easily; 3) a scalable DMA that can support unlimited TX/RX scattering/gathering data segments; 4) a reusable DMA that provides user defined TX information (or RX information) and TX message (or RX message) field; and 5) a high performance DMA that support unaligned segment data pointers and unlimited scattering/gathering data segments, so as to reduce extra memory copies by CPU. | 08-20-2009 |
20090262739 | NETWORK DEVICE OF PROCESSING PACKETS EFFICIENTLY AND METHOD THEREOF - A network device includes a first memory, a second memory, a receiver, a CPU, a transmitter, and a header cache controller (HCC). The HCC is coupled to the first memory and the second memory. The receiver, the CPU, and the transmitter access the first memory and the second memory via the HCC. The HCC can map an address of the first memory storing a header of a packet to an address of the second memory so as to store the header of the packet in the second memory. | 10-22-2009 |
20110103245 | BUFFER SPACE ALLOCATION METHOD AND RELATED PACKET SWITCH - A buffer space allocation method for a packet switch includes periodically performing a measurement process to obtain a plurality of measurement results at different times, each measurement result indicating a total size of accumulated packets in an output queue corresponding to one of a plurality of network ports of the packet switch, and adjusting a dedicated buffer space of the output queue according to the plurality of measurement results and a reserved space value for the dedicated buffer space. | 05-05-2011 |
20120166861 | METHOD FOR ADJUSTING CLOCK FREQUENCY OF A PROCESSING UNIT OF A COMPUTER SYSTEM AND RELATED DEVICE - A method for adjusting clock frequency of a processing unit of a computer system includes calculating a busyness ratio of the processing unit according to a status signal provided by the processing unit, determining whether the busyness ratio is in a busyness ratio range, when the busyness ratio is not in the busyness ratio range, determining whether a calculation result generated according to a clock frequency of the processing unit and a frequency difference is in a frequency range, and when the calculation result is in the frequency range, adjusting the clock frequency of the processing unit according to the calculation result and outputting the adjusted clock frequency to a clock generator, wherein the busyness ratio range, the frequency range and the frequency difference are decided according to an operation state of a peripheral unit of the computer system. | 06-28-2012 |
20130058319 | Network Processor - The present invention discloses a network processor for a broadband gateway. The network processor includes a host processor; a plurality of networking interfaces, corresponding to a plurality of networking technologies, respectively; and a network address translation (NAT) engine, for accelerating packet processing from a first networking interface to a second networking interface. | 03-07-2013 |
20130254433 | DIRECT MEMORY ACCESS SYSTEM AND METHOD USING THE SAME - The invention discloses a DMA system capable of being adapted to various interfaces. The DMA system includes the following advantages: 1) the software porting effort can be reduced when different interfaces are integrated into a SoC; 2) a flexible DMA that could provide protocol transparency and could be ported into different interfaces easily; 3) a scalable DMA that can support unlimited TX/RX scattering/gathering data segments; 4) a reusable DMA that provides user defined TX information (or RX information) and TX message (or RX message) field; and 5) a high performance DMA that support unaligned segment data pointers and unlimited scattering/gathering data segments, so as to reduce extra memory copies by CPU. | 09-26-2013 |
20130272311 | Communication Device and Related Packet Processing Method - The present invention discloses a communication device, including a first network interface, for receiving a plurality of packets composed of a plurality of first packets destined to a first communication device and a plurality of second packets, a first reordering engine, for reordering the plurality of first packets, outputting the plurality of reordered first packets, and outputting the plurality of second packets, a second reordering engine, for receiving the plurality of second packets from the first reordering engine, and reordering the plurality of second packets, a second network interface, for receiving the plurality of reordered first packets from the first reordering engine, and transmitting the plurality of reordered first packets to the first communication device, and a processing module, for processing the plurality of reordered second packets. | 10-17-2013 |
20140269298 | Network Processor and Method for Processing Packet Switching in Network Switching System - A network processor for processing packet switching in a network switching system is disclosed. The network processor includes a first memory for storing a first packet among a plurality of packets; a second memory for storing a second packet among the plurality of packets; and a memory selecting unit for selecting the first memory or the second memory for storing each of the plurality of packets according to whether a traffic of the network switching system is congested; wherein attributes of the first memory and the second memory are different. | 09-18-2014 |
20140376549 | PACKET PROCESSING APPARATUS AND METHOD FOR PROCESSING INPUT PACKET ACCORDING TO PACKET PROCESSING LIST CREATED BASED ON FORWARDING DECISION MADE FOR INPUT PACKET - A packet processing method includes receiving a forwarding decision made for an input packet; and creating a packet processing list of the input packet according to the forwarding decision. When the forwarding decision indicates that the input packet is required to undergo first packet processing operations, each including a common processing operation and an individual processing operation, to generate first output packets forwarded via first egress ports, respectively, first information indicative of the first egress ports is recorded in an egress port field of a first session of the packet processing list; second information indicative of the common processing operation shared by all of the first packet processing operations is recorded in a common processing field of the first session; and third information indicative of individual processing operations of the first packet processing operations is recorded in an individual processing field of the first session. | 12-25-2014 |