Patent application number | Description | Published |
20080265949 | CMOS DRIVING CIRCUIT - A CMOS driving circuit, wherein an output buffer stage with a transistor switch is added to the final buffer stage of a conventional CMOS driving circuit to drive a power transistor. The output buffer stage has two input terminals for DC input voltage, and uses the high voltage of a voltage converting circuit in a multi-voltage system as one DC input voltage. The driving load capacity of the CMOS driving circuit is improved by converting the higher of the two DC input voltages to a modulated driving voltage and outputting it via an output terminal, so that the on-resistance of a power transistor connected with the output buffer stage is lowered, the power consumption of the power transistor is reduced, the output capacity is improved, and the area of the power transistor is lowered with the same output power. | 10-30-2008 |
20080266917 | DC/DC CONVERTING SYSTEM - A DC/DC converting system, comprising: a DC/DC converter adapted to convert an input voltage to a second output voltage; and a charge pump adapted to provide an operation voltage to the DC/DC converter. According to embodiments of the present invention, a DC/DC converter having a large operation voltage range can be implemented by connecting a charge pump with a DC/DC converter and using the first output voltage of the charge pump as the operation voltage of the DC/DC converter. Moreover, by connecting at least one back-to-back diode switch between the power supply terminal and the first output terminal of the first DC/DC converting circuit of the charge pump, a first output voltage may be output stably as the operation voltage of the DC/DC converter when different input voltages are input to the power supply terminal. | 10-30-2008 |
20080290901 | Voltage Shifter Circuit - The present invention provides a voltage shifter circuit, in which a control circuit is used to control the pull-up circuit, so that the pull-up circuit is kept as off when the signal from the input signal source changes from a low voltage to a high voltage. Hence, the competition between the pull-up circuit and the pull-down circuit is avoided. The speed of the voltage shifter circuit is improved and the voltage shifter circuit can operate within a wider voltage range. The delay time of the pull-up circuit and the pull-down circuit is small and the duty cycle is small. In addition, since no direct current path is established, no current is wasted. Additionally, the voltage shifter circuit uses the second delayer to compensate the delay time between the pull-up circuit and the pull-down circuit and optimizes the duty cycle. | 11-27-2008 |
Patent application number | Description | Published |
20130122046 | REGULATORY FACTOR OF FOXP3 AND REGULATORY T CELLS AND USE THEREOF - Use of an ubiquitination pathway-related factor, its agonist or antagonist in the preparation of a composition for regulating FOXP3, IL-2, and/or IFN-γ activity, in which the ubiquitination pathway-related factor is selected from: Toll-like receptor, ubiquitin ligase, pro-inflammatory cytokine family receptor, and/or its coding sequence. The new type of regulatory factors can regulate regulatory T cells and immune system by regulating FOXP3, IL-2, and/or IFN-γ activity. The regulatory factors and their derivatives can also be used as immunoadjuvant for treating or preventing major diseases (such as, infectious diseases and tumor, etc). | 05-16-2013 |
20150073043 | USE OF PHOSPHORYLATION PATHWAY-RELATED FACTOR IN REGULATING FUNCTION OF REGULATORY T CELL - A method for the treatment and/or the prevention of a disease or a symptom related to dysfunction of regulatory T cell immunomodulation includes administering to a subject in need thereof compositions that regulate regulatory T cell immunomodulatory function, in which the compositions may be prepared by contacting starting materials with phosphorylation pathway-related factors, the agonists or the antagonists thereof. The phosphorylation pathway-related factors are selected from: proto-oncogene protein PIM1 and the coding sequence thereof. The regulation is achieved by regulating the activity of regulators of regulatory T cells selected from the group: FOXP3, IL-2, GITR, CTLA4, and a combination thereof. | 03-12-2015 |
Patent application number | Description | Published |
20110131552 | AUGMENTING VISUALIZATION OF A CALL STACK - In one embodiment, a method comprises the steps of obtaining software architecture information for describing software architecture of the software; parsing the software architecture information to generate a set of module objects, wherein the module objects correspond to software modules of the software; obtaining a call object of the software call stack, wherein the call object corresponds to a method or function executed when the software is running; comparing an invocation interface of the module object with the call object; and associating corresponding information of the module object with the call object of the software call stack according to a comparison result. | 06-02-2011 |
20120297168 | PROCESSING INSTRUCTION GROUPING INFORMATION - Processing instruction grouping information is provided that includes: reading addresses of machine instructions grouped by a processor at runtime from a buffer to form an address file; analyzing the address file to obtain grouping information of the machine instructions; converting the machine instructions in the address file into readable instructions; and obtaining grouping information of the readable instructions based on the grouping information of the machine instructions and the readable instructions resulted from conversion. Status of grouping and processing performed on instructions by a processor at runtime can be acquired dynamically, such that processing capability of the processor can be better utilized. | 11-22-2012 |
20130174127 | CONTROL FLOW ANALYSIS - A method for control flow analysis according to an embodiment of the present invention includes: acquiring an original function call tree of a program, wherein nodes of the original function call tree represent functions and a parent/child relation between the nodes represents a calling relation; generating a corresponding function dominator tree from the calling relation, wherein nodes of the function dominator tree represent the functions and a parent/child relation between the nodes represents a dominator relation, wherein a first function dominates a second function if all the invocations to the second function are originated by the first function; and simplifying the original function call tree according to the function dominator tree so as to obtain a simplified function call tree. According to an embodiment of the present invention, the function call tree for control flow analysis can be simplified. | 07-04-2013 |
Patent application number | Description | Published |
20100237891 | Method, apparatus and system of parallel IC test - A method, apparatus and system for integrated circuit testing, wherein a plural number of devices under test (DUTs) and a plural number of comparison apparatuses are placed on a common substrate. The DUTs all operate under the same input stimulation and each produce its own operation output. The outputs are compared by the comparison apparatuses to generate comparison characteristics which are used to filter-out the failed devices. This invention lowers the testing cost, shortens time to product mass-production, and lowers the miss rate of failed devices passed as good ones. | 09-23-2010 |
20110231616 | DATA PROCESSING METHOD AND SYSTEM - A configurable multi-core structure is provided for executing a program. The configurable multi-core structure includes a plurality of processor cores and a plurality of configurable local memory respectively associated with the plurality of processor cores. The configurable multi-core structure also includes a plurality of configurable interconnect structures for serially interconnecting the plurality of processor cores. Further, each processor core is configured to execute a segment of the program in a sequential order such that the serially-interconnected processor cores execute the entire program in a pipelined way. In addition, the segment of the program for one processor core is stored in the configurable local memory associated with the one processor core along with operation data to and from the one processor core. | 09-22-2011 |
20110238917 | HIGH-PERFORMANCE CACHE SYSTEM AND METHOD - A digital system is provided for high-performance cache systems. The digital system includes a processor core and a cache control unit. The processor core is capable of being coupled to a first memory containing executable instructions and a second memory with a faster speed than the first memory. Further, the processor core is configured to execute one or more instructions of the executable instructions from the second memory. The cache control unit is configured to be couple to the first memory, the second memory, and the processor core to fill at least the one or more instructions from the first memory to the second memory before the processor core executes the one or more instructions, Further, the cache control unit is also configured to examine instructions being filled from the first memory to the second memory to extract instruction information containing at least branch information, to create a plurality of tracks based on the extracted instruction information; and to fill the at least one or more instructions based on one or more tracks from the plurality of instruction tracks, | 09-29-2011 |
20110264894 | BRANCHING PROCESSING METHOD AND SYSTEM - A method is provided for controlling a pipeline operation of a processor. The processor is coupled to a memory containing executable computer instructions. The method includes determining a branch instruction to be executed by the processor, and providing both an address of a branch target instruction of the branch instruction and an address of a next instruction following the branch instruction in a program sequence. The method also includes determining a branch decision with respect to the branch instruction based on at least the address of the branch target instruction provided, and selecting at least one of the branch target instruction and the next instruction as a proper instruction to be executed by an execution unit of the processor, based on the branch decision and before the branch instruction is executed by the execution unit, such that the pipeline operation is not stalled whether or not a branch is taken with respect to the branch instruction. | 10-27-2011 |
20120191967 | CONFIGURABLE DATA PROCESSING SYSTEM AND METHOD - A reconfigurable data processing platform is disclosed. The reconfigurable data processing platform includes a reconfigurable universal data processing module, a configuration memory, and a reconfiguration control unit. The reconfigurable universal data processing module contains a plurality of basic units each capable of being configured to perform a unit of at least one of a logic operation and an arithmetic operation. The configuration memory is coupled to the reconfigurable universal data processing module to provide configuration information to be used to configure the plurality of basic units. Further, the reconfiguration control unit is coupled to the reconfigurable universal data processing module and the configuration memory to provide control signals for configuration of the plurality of basic units. | 07-26-2012 |
20120265951 | WIDE BANDWIDTH READ AND WRITE MEMORY SYSTEM AND METHOD - A memory device includes a first memory array, a first read port, a second read port, and a control input port. The first memory array contains a plurality of memory cells arranged in an array configuration. The first read port is configured to read first data from a single memory cell during a single read cycle, and the second read port is configured to read second data from a group of memory cells controlled by a common word line. Further, the control input is configured to receive a mode signal indicating a functional mode for the memory device including a first read mode and a second read mode. When the mode signal indicates the first read mode, the first read port is used to read the first data. When the mode signal indicates the second read mode, the first read port is used to read out the first data and the second read port is used to read the second data. | 10-18-2012 |
20120278590 | RECONFIGURABLE PROCESSING SYSTEM AND METHOD - A reconfigurable processor is provided. The reconfigurable processor includes a plurality of functional blocks configured to perform corresponding operations. The reconfigurable processor also includes one or more data inputs coupled to the plurality of functional blocks to provide one or more operands to the plurality of functional blocks, and one or more data outputs to provide at least one result outputted from the plurality of functional blocks. Further, the reconfigurable processor includes a plurality of devices configured to inter-connect the plurality of functional blocks such that the plurality of functional blocks are independently provided with corresponding operands from the data inputs and individual results from the plurality of functional blocks are independently feedback as operands to the plurality of functional blocks to carry out one or more operation sequences | 11-01-2012 |
20130111137 | PROCESSOR-CACHE SYSTEM AND METHOD | 05-02-2013 |
20130185545 | HIGH-PERFORMANCE CACHE SYSTEM AND METHOD - A digital system includes a processor core and a cache control unit. The processor core can be coupled to a first memory containing data and a second memory with a faster speed than the first memory, and is configured to execute a segment of instructions having at least one instruction accessing the data from the second memory using a base register. The cache control unit is configured to be coupled to the first memory, the second memory, and the processor core to fill the data from the first memory to the second memory before the processor core executes the instruction accessing the data, and is further configured to examine the segment of instructions to extract instruction information containing at least data access instruction information and last register updating instruction information and to create a track corresponding to the segment of instructions based on the extracted instruction information. | 07-18-2013 |
20130339611 | HIGH-PERFORMANCE CACHE SYSTEM AND METHOD - A digital system is provided for high-performance cache systems. The digital system includes a processor core and a cache control unit. The processor core is capable of being coupled to a first memory containing executable instructions and a second memory with a faster speed than the first memory. Further, the processor core is configured to execute one or more instructions of the executable instructions from the second memory. The cache control unit is configured to be couple to the first memory, the second memory, and the processor core to fill at least the one or more instructions from the first memory to the second memory before the processor core executes the one or more instructions. Further, the cache control unit is also configured to examine instructions being filled from the first memory to the second memory to extract instruction information containing at least branch information, to create a plurality of tracks based on the extracted instruction information; and to fill the at least one or more instructions based on one or more tracks from the plurality of instruction tracks. | 12-19-2013 |
20140337582 | HIGH-PERFORMANCE CACHE SYSTEM AND METHOD - A digital system is provided for high-performance cache systems. The digital system includes a processor core and a cache control unit. The processor core is capable of being coupled to a first memory containing executable instructions and a second memory with a faster speed than the first memory. Further, the processor core is configured to execute one or more instructions of the executable instructions from the second memory. The cache control unit is configured to be couple to the first memory, the second memory, and the processor core to fill at least the one or more instructions from the first memory to the second memory before the processor core executes the one or more instructions. Further, the cache control unit is also configured to examine instructions being filled from the first memory to the second memory to extract instruction information containing at least branch information, to create a plurality of tracks based on the extracted instruction information; and to fill the at least one or more instructions based on one or more tracks from the plurality of instruction tracks. | 11-13-2014 |
Patent application number | Description | Published |
20120316200 | PYRIDONE DERIVATIVES - The present invention is directed to novel phenylpyridone derivative compounds. The compounds act as a melanin concentrating hormone receptor antagonists, and can be useful in preventing, treating or acting as a remedial agent for various circular system diseases, nervous system diseases, metabolic diseases, genital diseases, respiratory diseases and digestive diseases. | 12-13-2012 |
20140045746 | ANTIDIABETIC TRICYCLIC COMPOUNDS - Novel compounds of the structural formula (I), and the pharmaceutically acceptable salts thereof, are agonists of G-protein coupled receptor 40 (GPR40) and may be useful in the treatment, prevention and suppression of diseases mediated by the G-protein-coupled receptor 40. The compounds of the present invention may be useful in the treatment of Type 2 diabetes mellitus, and of conditions that are often associated with this disease, including obesity and lipid disorders, such as mixed or diabetic dyslipidemia, hyperlipidemia, hypercholesterolemia, and hypertriglyceridemia. | 02-13-2014 |
Patent application number | Description | Published |
20100004775 | METHOD AND SYSTEM FOR DEFECT DETECTION IN MANUFACTURING INTEGRATED CIRCUITS - Method and system for defect detection in manufacturing integrated circuits. In an embodiment, the invention provides a method for identifying one or more sources for possible causing manufacturing detects in integrated circuits. The method includes a step for providing a plurality of semiconductor substrates. The method includes a step for processing the plurality of semiconductor substrates in a plurality of processing steps using a plurality of processing tools. The method additionally includes a step for providing a database, which includes data associated with the processing of the plurality of semiconductor substrates. The method further includes a step for testing the plurality of semiconductor wafers after the processing of the plurality of semiconductor substrates. Additionally, the method includes a step for detecting at least one defect characteristic associated with the plurality of the semiconductor substrates that have been processed. Moreover, the method includes a step for identifying a set of processing steps. For example, the set of processing step are possibly associated with the defect characteristic. | 01-07-2010 |
20120023464 | AUTOMATIC IDENTIFICATION OF SYSTEMATIC REPEATING DEFECTS IN SEMICONDUCTOR PRODUCTION - A method includes capturing an image of the pattern using one or more scans across a surface of the partially completed wafer. The method includes processing information associated with the captured image of the pattern in a first format (e.g., pixel domain) into a second format, e.g., transform domain. The method includes determining defect information associated with the image of the pattern in the second format and processing the defect information (e.g., wafer identification, product identification, layer information, x-y die scanned) to identify at least one defect associated with a spatial location of a repeating pattern on the partially completed wafer provided by a reticle. The method includes identifying the reticle associated with the defect and a stepper associated with the reticle having the defect and ceasing operation of the stepper. The damaged reticle is replaced, and the process resumes using a replaced reticle. | 01-26-2012 |
Patent application number | Description | Published |
20120304721 | COLD-ROLLING METHOD FOR PREVENTING FRACTURE OF HIGH-SILICON STRIP STEEL - A cold-rolling method for preventing fracture of high-silicon strip steel, characterized in that the high-silicon strip steel has a Si content ≧2.3 wt %, and at the beginning of cold-rolling, the temperature of inlet strip steel is above 45° C.; during the cold-rolling process, an emulsion liquid is sputtered to the strip steel, a flow rate of the emulsion liquid is 3500 L/min at the inlet in rolling direction, a flow rate of the emulsion liquid is 1500-4000 L/min at an outlet in the rolling direction, and the temperature of the strip steel is maintained above 45° C. under the precondition to guarantee technological lubrication. The cold-rolling method of the invention might prevent fracture of a head portion and a tail portion of the strip steel, raise the rate of finished products, and increase production efficiency. | 12-06-2012 |
20150013846 | Method for Producing Silicon Steel Normalizing Substrate - A method for producing a silicon steel normalizing substrate comprises steelmaking, hot rolling and normalizing steps. A normalizing furnace is used in the normalizing step, and along a moving direction of strip steel, the normalizing furnace sequentially comprises: a preheating section, a nonoxidizing heating section, a furnace throat, furnace sections for subsequent normalizing processing, and a delivery seal chamber. Furnace pressures of the normalizing furnace are distributed as follows: the furnace pressure of a downstream furnace section adjacent to the furnace throat along the moving direction of the strip steel is the highest, the furnace pressure decreases gradually from the furnace section with the highest furnace pressure to a furnace section in an inlet direction of the normalizing furnace, and the furnace pressure decreases gradually from the furnace section with the highest furnace pressure to a furnace section in an outlet direction of the normalizing furnace. | 01-15-2015 |
Patent application number | Description | Published |
20120261669 | PHOTO DETECTOR CONSISTING OF TUNNELING FIELD-EFFECT TRANSISTORS AND THE MANUFACTURING METHOD THEREOF - The present invention belongs to the technical field of optical interconnection and relates to a photo detector, in particular to a photo detector consisting of tunneling field-effect transistors. | 10-18-2012 |
20130065365 | Method for Manufacturing Semiconductor Substrate of Large-power Device - The invention belongs to the technical field of high-voltage, large-power devices and in particular relates to a method for manufacturing a semiconductor substrate of a large-power device. According to the method, the ion implantation is carried out on the front face of a floating zone silicon wafer first, then a high-temperature resistant metal is used as a medium to bond the back-off floating zone silicon wafer, and a heavily CZ-doped silicon wafer forms the semiconductor substrate. After bonding, the floating zone silicon wafer is used to prepare an insulated gate bipolar transistor (IGBT), and the heavily CZ-doped silicon wafer is used as the low-resistance back contact, so the required amount of the floating zone silicon wafers used is reduced, and production cost is lowered. Meanwhile, the back metallization process is not required after bonding, so the processing procedures are simplified, and the production yield is enhanced. | 03-14-2013 |
20130149824 | METHOD FOR MANUFACTURING A TUNNELING FIELD EFFECT TRANSISTOR WITH A U-SHAPED CHANNEL - The present invention belongs to the technical field of semiconductor device manufacturing and specifically relates to a method for manufacturing a tunneling field effect transistor with a U-shaped channel. The U-shaped channel can effectively extend the transistor channel length, restrain the generation of leakage current in the transistor, and decrease the chip power consumption. The method for manufacturing a tunneling field effect transistor with a U-shaped channel put forward in the present invention is capable of realizing an extremely narrow U-shaped channel, overcoming the alignment deviation introduced by photoetching, and improving the chip integration degree. | 06-13-2013 |
20130149848 | METHOD FOR MANUFACTURING VERTICAL-CHANNEL TUNNELING TRANSISTOR - The present invention belongs to the technical field of semiconductors and specifically relates to a method for manufacturing a vertical-channel tunneling transistor. In the present invention, the surrounding gate gate structure improves the control capacity of the gate and the source of narrow band gap material can enhance the device driving current. The method for manufacturing a vertical-channel tunneling transistor put forward by the present invention capable of controlling the channel length precisely features simple process, easy control and reduction of production cost. | 06-13-2013 |
20130162959 | Brightness-adjustable Light-emitting Device and Array and the Manufacturing Methods Thereof - The present invention belongs to the technical field of semiconductor devices and relates to a brightness-adjustable illuminator and an array and the manufacturing methods thereof. The illuminator is comprised of a semiconductor substrate, a MOSFET and a light-emitting diode that are located on the semiconductor substrate. The light-emitting diode (LED) and the control element (MOSFET) thereof are integrated on the same chip, so a single chip is capable of realizing the image transmission. An illuminator array may consist of a plurality of illuminators. Meanwhile, the invention also discloses a method for manufacturing the illuminator. Therefore, the projection equipment manufactured by the technology of the present invention has the advantages of small size, portability, low power consumption, etc. Furthermore, the use of the integrated circuit chip greatly simplifies the system of the projection equipment, reduces the production cost and greatly enhances the pixel quality and brightness. | 06-27-2013 |
20130237009 | METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR DEVICE - The present invention belongs to the technical field of semiconductor device manufacturing, and specifically relates to a method for manufacturing a gate-control diode semiconductor device. The present invention manufactures gate-control diode semiconductor devices through a low-temperature process, features a simple process, low manufacturing cost, and capacity of manufacturing gate-control diode devices able to reduce the chip power consumption through advantages of high driving current and small sub-threshold swing. The method for manufacturing a gate-control diode semiconductor device proposed by the present invention is especially applicable to the manufacturing of reading & writing devices having flat panel displays and phase change memory, and semiconductor devices based on flexible substrates. | 09-12-2013 |
20130237010 | METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR MEMORY DEVICE - The present invention belongs to the technical field of semiconductor device manufacturing, and specifically discloses a method for manufacturing a gate-control diode semiconductor storage device. The present invention manufactures gate-control diode semiconductor memory devices through a low-temperature process featuring a simple process, low manufacturing cost and capacity of manufacturing gate-control diode memory devices with a high driving current and small sub-threshold swing. The method for manufacturing a gate-control diode semiconductor memory device proposed by the present invention is especially applicable to the manufacturing of flat panel displays and phase change memories and memory devices based on flexible substrate. | 09-12-2013 |
20130341696 | METAL-OXIDE-SEMICONDUCTOR (MOS) TRANSISTOR STRUCTURE INTEGRATED WITH A RESISTANCE RANDOM ACCESS MEMORY (RRAM) AND THE MANUFACTURING METHODS THEREOF - The present invention belongs to the technical field of semiconductor memories, in particular to a metal oxide semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM). The MOS transistor structure comprises a MOS transistor and a RRAM formed on a substrate, wherein a gate dielectric layer of said MOS transistor extends to the surface of a drain region of said MOS transistor; and the part of the gate dielectric layer on the surface of the drain region of said MOS transistor faults a resistance-variable storage layer of said RRAM. In this invention, the high-quality dielectric layer of the MOS transistor and the resistance-variable storage layer of the RRAM are obtained by primary atomic layer deposition which integrates the RRAM and MOS transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient. | 12-26-2013 |
20130341697 | TUNNEL TRANSISTOR STRUCTURE INTEGRATED WITH A RESISTANCE RANDOM ACCESS MEMORY (RRAM) AND A MANUFACTURING METHOD THEREOF - The invention relates to the technical field of semiconductor memories, in particular to a tunnel transistor structure integrated with a resistance random access memory and a manufacturing method thereof. The tunnel transistor structure in the present invention comprises a semiconductor substrate, and a tunnel transistor and a resistance random access memory formed on the semiconductor substrate, wherein the gate dielectric layer of the tunnel transistor extends to the surface of a drain region of the tunnel transistor; the part of the gate dielectric layer on the surface of the drain region of the tunnel transistor forms the resistance-variable storage layer of the resistance random access memory. In this invention, the high-quality gate dielectric layer of the tunnel transistor and the resistance-variable storage layer of the resistance random access memory are obtained by primary atomic layer deposition which integrates the resistance random access memory and tunnel transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient. | 12-26-2013 |
20140034891 | SEMICONDUCTOR MEMORY STRUCTURE AND ITS MANUFACTURING METHOD THEREOF - The present invention belongs to the technical field of microelectronic devices, specifically relates to a semiconductor memory structure and its manufacturing method thereof. The semiconductor memory structure which carries out erasing, writing and reading operation on the phase change memory or the resistance change memory through a tunneling field-effect transistor is formed, for one hand, the high current passed through the tunneling field-effect transistor when the p-n junction the biased positively, meeting the high current requirements for erasing of and writing of the phase change memory and the resistance change memory, and on the other hand, Vertical structure of the field-effect transistor can greatly improve the density of memory devices arrays. The present invention also discloses a method, which is very suitable for the memory chips, for the manufacturing of the semiconductor memory structure using self-aligned process. | 02-06-2014 |
20140167134 | SELF-ALIGNED VERTICAL NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - The present invention belongs to the technical field of semiconductor memory devices and specifically relates to a self-aligned vertical nonvolatile semiconductor memory device, Including: a semiconductor substrate, a drain region of a first doping type, two source regions of a second doping type, a stacked gate used to capture electrons; wherein the drain region, the two source regions and the stacked gate form two tunneling field effect transistors (TFETs) sharing one gate and one drain, the drain region current of each of the TFET is affected by the quantity and distribution of the charges in the stacked gate used to capture electrons, the drain is buried in the semiconductor substrate, the source regions above the drain region are separated from the drain through a channel and separated form each other through a region of the first doping type. The semiconductor memory device of the present invention features small unit area and simple manufacturing process. The memory chip using the present invention is of low manufacturing cost and high storage density. | 06-19-2014 |
Patent application number | Description | Published |
20130338993 | NESTED EMULATION AND DYNAMIC LINKING ENVIRONMENT - Various embodiments include nested emulation for a source application and source emulator. Duplicate source ISA libraries redirect the source emulator library calls to a target library, thereby forcing the native emulator through proper emulation channels between first and second ISAs. Other embodiments concern accelerating dynamic linking by determining certain function calls that, rather than being processed through emulation of PLT code, are instead directly called without the need for PLT code translation. Some embodiments address both nested emulation and accelerated dynamic linking but other embodiments include one of nested emulation and accelerated dynamic linking. Other embodiments are described herein. | 12-19-2013 |
20140040921 | ISA BRIDGING WITH CALLBACK - Methods, apparatuses and storage medium associated with ISA bridging with callback, are disclosed. In various embodiments, at least one computer-readable storage medium may include instructions configured to enable a target device with a target ISA, in response to execution of the instructions, to provide an ISA bridging layer to the target device to facilitate a library service to callback a callback function of an application. The library service may be implemented for the target ISA, and the application may be implemented at least partially for a source ISA that may be different from the target ISA. The ISA bridging layer may include a source ISA emulator and a library emulator configured to cooperate to enable the application to call the library service, and the library service to callback the callback function, across the two instruction set architectures. Other embodiments may be disclosed or claimed. | 02-06-2014 |
20140046649 | ISA BRIDGING INCLUDING SUPPORT FOR CALL TO OVERIDDING VIRTUAL FUNCTIONS - Methods, apparatuses and storage medium associated with ISA bridging with support for virtual functions, are disclosed. In embodiments, at least one computer-readable storage medium may include instructions configured to enable a target device with a target ISA, in response to execution, to provide an ISA bridging layer to the target device to facilitate a library service of a library of the target device to call a virtual function of the library, while servicing an application operating on the target device, where the application has an overriding implementation. The ISA bridging layer may include a loader configured to load the application for execution, and as part of loading the application, detect the virtual function and modify a virtual function table of the application to enable the call. Other embodiments may be disclosed or claimed. | 02-13-2014 |
Patent application number | Description | Published |
20110310244 | SYSTEM AND METHOD FOR DETECTING A DEFECT OF A SUBSTRATE - A system and a method for detecting defects of a substrate are provided. The system includes: a first illuminating component, disposed at one side of the substrate and adapted to emit diffused light to the substrate; a first imaging component, disposed at the other side of the substrate and adapted to scan the substrate by sensing light emitted by the first illuminating component and transmitted through the substrate, the first illuminating component and the first imaging component constructing a first detection channel; and a transport module, adapted to produce relative motion between the substrate, and the first illuminating component and the first imaging component. | 12-22-2011 |
20120044344 | METHOD AND SYSTEM FOR DETECTING DEFECTS OF TRANSPARENT SUBSTRATE - A method and a system for detecting defects of a transparent substrate are provided. The system includes: a plurality of detection channels, each of which includes an illumination component for providing illumination to the substrate and an imaging component for scanning the substrate to provide image of the substrate; a transport module, for producing relative motion between the substrate and the illumination components and the imaging components included in the plurality of detection channels; and a controlling module, for controlling the illumination components and the imaging components included in the plurality of detection channels so that at least two illumination components of the illumination components included in the plurality of detection channels provide illumination to the substrate alternately, and the imaging component included in any of the plurality of detection channels scans the substrate when the illumination component included in that detection channel illuminates the substrate, wherein the imaging components included in at least two detection channels of the plurality of detections channels are the same imaging component. The method and system described by the present invention is capable of discriminating real defects from fake defects which enables substrate to be inspected with free of cleaning. | 02-23-2012 |
20120105624 | METHOD AND DEVICE FOR DEFECT INSPECTION IN SEPARATED TRANSPARENT AND/OR SEMI-TRANSPARENT BODY - An apparatus and a method for detecting a defect of a separated low rigidity transparent or translucent body, wherein an image acquiring device includes: a first conveyer and a second conveyer to convey a separated low rigidity transparent or translucent body; a transparent bridge disposed between a first conveyer and a second conveyer along a transport path of the separated low rigidity transparent or translucent body, the transparent bridge having a top surface; an illuminating unit disposed on one side of the transparent bridge and configured to project diffusive light onto the top surface of the transparent bridge by transmitting through the transparent bridge; and an image pickup unit disposed on the other side of the transparent bridge and configured to receive light projected from the illuminating unit and transmitting through the separated low rigidity transparent or translucent body to form an image when the separated low rigidity transparent or translucent body enters the top surface of the transparent bridge. With the apparatus and the method, it is possible to detect a defect of the separated low rigidity transparent or translucent body. | 05-03-2012 |
20120133762 | METHOD AND SYSTEM FOR DETECTING AND CLASSIFYING A DEFECT OF A SUBSTRATE - A method and system for detecting and classifying a defect of a substrate, the system including a first channel, including a first illuminating unit to irradiate a light to a substrate and a first imaging unit to take images by sensing a light from the substrate when it is irradiated; a second channel, including a second illuminating unit to irradiate a light to the substrate and a second imaging unit to take images by sensing a light from the substrate when it is irradiated; an image constructing module to construct two images of the substrate using the images of the first and second imaging units respectively; and an image processing module to detect, when the substrate has a defect, that the defect is a defect on or in the substrate, based on a relationship of positions where the defect of the substrate appears in the two images of the substrate. | 05-31-2012 |
20140314593 | PUMP - A pump includes a drive assembly having a drive shaft rotatable about a drive axis, and an eccentric coupled to the drive shaft for rotation therewith. The eccentric includes a shaft portion defining an eccentric axis that is offset from the drive axis. The shaft portion includes a shaft end defining a first alignment feature. A piston is rotatably coupled to the shaft portion and defines a second alignment feature. A cylinder reciprocatingly receives the piston. Positioning the first alignment feature in a predetermined orientation with respect to the second alignment feature locates the piston in one of a top-dead-center position and a bottom-dead-center position with respect to the cylinder. | 10-23-2014 |
20140347657 | ILLUMINATION SYSTEM FOR DETECTING THE DEFECT IN A TRANSPARENT SUBSTRATE AND A DETECTION SYSTEM INCLUDING THE SAME - An illumination device for providing near isotropic illumination, and particularly an illumination system for detecting the defect in a transparent substrate and a detection system including the same are presented, An illumination system includes: an illumination system for detecting the defect in a transparent substrate, including light source receptacle in bar shape; first spot light sources, each emitting a respective first light, the respective first lights being substantially parallel to each other and the first spot light sources being arranged to a first line of spot light sources along the longitudinal direction of the receptacle; and second spot light sources, each emitting a respective second light, the respective second lights being substantially parallel to each other and the second spot light sources being arranged to a second line of spot light sources along the longitudinal direction of the receptacle. | 11-27-2014 |
Patent application number | Description | Published |
20100010053 | COMPOUNDS - The present invention relates to novel oxadiazole derivatives having pharmacological activity, processes for their preparation, pharmaceutical compositions containing them and their use in the treatment of various disorders. | 01-14-2010 |
20100029729 | COMPOUNDS - The present invention relates to novel oxadiazole derivatives having pharmacological activity, processes for their preparation, pharmaceutical compositions containing them and their use in the treatment of various disorders. | 02-04-2010 |
20110086839 | COMPOUNDS - The present invention relates to novel oxadiazole derivatives having pharmacological activity, processes for their preparation, pharmaceutical compositions containing them and their use in the treatment of various disorders. | 04-14-2011 |
20110269738 | COMPOUNDS - The present invention relates to novel compounds having pharmacological activity, processes for their preparation, pharmaceutical compositions containing them and their use in the treatment of various disorders. | 11-03-2011 |
20120094979 | THIAZOLE OR THIADIZALOE DERIVATIVES FOR USE AS SPHINGOSINE 1-PHOSPHATE 1 (S1P1) RECEPTOR AGONISTS - Thiazole or thiadizaloe derivatives of formula (I) or pharmaceutical salts thereof having pharmacological activity, processes for their preparation, pharmaceutical compositions containing them and their uses in the treatment of various disorders mediated by S1P1 receptor are disclosed. | 04-19-2012 |
20120101123 | COMPOUNDS - The present invention relates to novel compounds having pharmacological activity, processes for their preparation, pharmaceutical compositions containing them and their use in the treatment of various disorders. | 04-26-2012 |
20120101124 | 1,2,4-OXADIAZOL DERIVATIVES, THEIR PHARMACEUTICAL COMPOSITIONS AND THEIR USE AS SPHINGOSINE 1-PHOSPHATE 1 RECEPTOR AGONISTS - 1,2,4-Oxadiazol derivatives represented by formula (I) useful as sphingosine 1-phosphate 1 (S1P1) receptor agonists, processes for their preparation, pharmaceutical compositions containing them and their use in the treatment of various disorders mediated via S1P1 receptor are disclosed. | 04-26-2012 |
20120101134 | 5-MEMBERED HETEROARYL DERIVATIVES USED AS SPHINGOSINE 1-PHOSPHATE RECEPTOR AGONISTS - 5-membered heteroaryl derivatives of formula (I) or salts thereof, processes for their preparation, pharmaceutical compositions containing them and their uses in the treatment of various disorders mediated by S1P1 receptors are disclosed. | 04-26-2012 |
20120101136 | 5-MEMBERED HETEROARYL DERIVATIVES USED AS SPHINGOSINE 1- PHOSPHATE RECEPTOR AGONISTS - 5-membered heteroaryl derivatives of formula (I) or salts thereof, processes for their preparation, pharmaceutical compositions containing them and their uses in the treatment of various disorders mediated by S1P1 receptors are disclosed. | 04-26-2012 |
20120283297 | OXADIAZOLE SUBSTITUTED INDAZOLE DERIVATIVES FOR USE AS SPHINGOSINE 1-PHOSPHATE 1 (S1P1) RECEPTOR AGONISTS - Oxadiazole substituted indazole derivatives of formula (I) or pharmaceutical salts thereof having pharmacological activity, processes for their preparation, pharmaceutical compositions containing them and their uses in the treatment of various disorders mediated by S1P1 receptors are disclosed. | 11-08-2012 |
20130012491 | PYRIMIDINE DERIVATIVES FOR USE AS SPHINGOSINE 1-PHOSPHATE 1 (S1P1) RECEPTOR AGONISTS - Disclosed are pyrimidine derivatives for use as a sphingosine 1-phosphate 1 (S1P1) receptor agonists, processes for their preparation, pharmaceutical compositions containing them and their use in the treatment of conditions or diseases mediated by S1P1 receptors, particularly multiple sclerosis. | 01-10-2013 |
Patent application number | Description | Published |
20130163612 | REFRAMING CIRCUITRY WITH VIRTUAL CONTAINER DROP AND INSERT FUNCTIONALITY TO SUPPORT CIRCUIT EMULATION PROTOCOLS - Reframing circuitry controls communications between a physical layer device and a link layer device. In a first direction of communication, the reframing circuitry receives a container frame with the container frame having a first arrangement of columns, and outputs a virtual container frame that includes a modified version of the container frame received by the reframing circuitry, with the modified version of the container frame having a second arrangement of columns different than the first arrangement of columns. For example, the reframing circuitry in generating the modified version of the container frame may remove a path overhead column of the container frame and replace that path overhead column with a stuff column in the modified version of the container frame. The virtual container frame may be configured to include the path overhead column that was removed from the container frame in generating the modified version of the container frame. | 06-27-2013 |
20130250850 | BASE STATION TIMING CONTROL USING SYNCHRONOUS TRANSPORT SIGNALS - A base station of a wireless system comprises a local clock source and timing circuitry coupled to the local clock source. The timing circuitry is configured to adjust at least one parameter of the local clock source based at least in part on timing information extracted from designated portions of each of one or more frames of a synchronous transport signal received in the base station. The base station may further comprise a physical layer device, such as a mapper, configured to extract the timing information from the designated portions of each of the one or more frames of the synchronous transport signal. The designated portions of the one or more frames of the synchronous transport signal from which the timing information is extracted may comprise designated overhead bytes of the one or more frames, such as, for example, transport overhead (TOH) bytes. | 09-26-2013 |
20140119389 | INTERFACE FOR ASYNCHRONOUS VIRTUAL CONTAINER CHANNELS AND HIGH DATA RATE PORT - Data rate justification circuitry adapted to control one or more communications between a physical layer device and a link layer device. In a first direction of communication, the data rate justification circuitry is configured to receive first virtual container data from the physical layer device over two or more asynchronous virtual container channels, and to synchronize the first virtual container data and aggregate the first virtual container data for transmission to the link layer device over a high data rate port. In a second direction of communication, the data rate justification circuitry is configured to receive second virtual container data from the link layer device over the high data rate port, and to decode data rate information associated with the second virtual container data and separate the second virtual container data for transmission to the physical layer device over the two or more asynchronous virtual container channels. | 05-01-2014 |
Patent application number | Description | Published |
20110078545 | Frame Boundary Detection and Synchronization System for Data Stream Received by Ethernet Forward Error Correction Layer - The present invention discloses a frame boundary detection system and a synchronization system for a data stream received by an Ethernet Forward Error Correction layer. The frame boundary detection system includes a shifter, two descramblers, a syndrome generator and trapper. The error trapper includes a big-little endian mode controller for controlling the big-little endian conversion of the error trapper. If the error trapper operates in the big endian mode, the error trapper implements the function of the syndrome generator, operates at the same time with the syndrome generator, and performs a second FEC check, wherein when the shifter performs the FEC check by intercepting data with a length of one frame plus A bits, two start positions of the frame can be verified, where A is a positive integer less than a length of one frame. The invention can improve the frame boundary detection speed and the frame synchronization speed, and increase only a few hardware overheads. | 03-31-2011 |
20120159416 | Constructing a Clock Tree for an Integrated Circuit Design - A method and apparatus for constructing a clock tree for an integrated circuit design is disclosed, the method comprising: extracting the path delays between the sequential devices in a placed netlist by performing timing analysis on the placed netlist; and constructing a clock tree for driving the sequential devices according to the path delays between the sequential devices so as to make the sum of the products of the timing delay between any two sequential devices and a clock tree branch weight of the two sequential devices minimum, wherein the clock tree branch weight of the two sequential devices is positively correlated with the number of clock tree levels from the branch point of the clock tree relative to the two sequential devices to the two sequential devices. | 06-21-2012 |
20120179950 | Method and System for Detecting the Frame Boundary of a Data Stream Received in Forward Error Correction Layer in the Ethernet - The present invention discloses a method and system for detecting the frame boundary of a data stream received in Forward Error Correction layer in the Ethernet. The present invention can increase the speed of frame boundary detection and the speed of frame synchronization without adding any overheads of hardware. | 07-12-2012 |
Patent application number | Description | Published |
20130163306 | One-Time Programmable Memory Cell, Memory and Manufacturing Method Thereof - The present invention pertains to the technical field of one-time programmable memory (OTP), and in particular to a one-time programmable memory unit, OTP, and method of fabricating the same. The OTP unit comprises a lower electrode, an upper electrode and a storage medium layer placed between the upper electrode and the lower electrode, the storage medium layer comprises a first metal oxide layer and a second metal oxide layer, wherein an adjoining area for programming is formed between the first metal oxide layer and the second metal oxide layer. The OTP comprises a plurality of the above-described one-time programmable memory units arranged in rows and columns. The OTP unit and the OTP have such characteristics as low programming voltage, small unit area, being able to integrate into a back-end structure of integrated circuit, great process flexibility, and the method of fabricating the OTP unit and the OTP is relatively simple and low in cost. | 06-27-2013 |
20130193397 | High Consistency Resistive Memory and Manufacturing Method Thereof - The present invention relates to the technical field of memories, and in particular to a highly-consistent resistive memory and method of fabricating the same. The resistive memory comprises: a lower electrode which is formed in a first dielectric layer by patterning; a second dielectric layer formed on the lower electrode and the first dielectric layer and provided with an opening for exposing the lower electrode to perform patterning; an edge wall formed in the opening of the second dielectric layer for covering a border area of the lower electrode and the first dielectric layer so that only the middle area of the lower electrode is partially or totally exposed; a storage medium layer formed by performing oxidization with the second dielectric layer and the edge wall as mask; and an upper electrode. The resistive memory exhibits good consistency and high reliability; moreover, unit size is mall, which is advantageous for improving storage characteristic. When an array of memories is formed by the resistive memories, a good consistency is obtained among multiple resistive memories. | 08-01-2013 |
20140103281 | Resistive Memory Based on TaOx Containing Ru Doping and Method of Preparing the Same - The present invention pertains to the technical field of semi-conductor memory. More particularly, the invention relates to a resistive memory based on TaO | 04-17-2014 |
20140113428 | Method for Integrating MnOz Based Resistive Memory with Copper Interconnection Back-End Process - The present invention pertains to the technical field of semiconductor memory. More particularly, the invention relates to a method for integrating MnO | 04-24-2014 |
Patent application number | Description | Published |
20110035577 | ENHANCED DIGITAL RIGHT MANAGEMENT FRAMEWORK - Machine-readable media, methods, apparatus and system for enhanced digital right management framework are described. A server platform may receive a request of downloading content and first attestation information from a client platform. The server platform may examine if the client platform attests to a client platform characteristic that affects integrity of the client platform by using the attestation information, and then encrypt and download the content to the client platform if the client platform attests to the client platform characteristic. The server platform may further receive a request of viewing the content and second attestation information from the client platform. The server platform may then examine if the client platform attests to its integrity by using the second attestation information; and then send a content key to the client platform if the client platform attests to its integrity, so that the client platform can decrypt and view the content. | 02-10-2011 |
20140198851 | LEVERAGING ENCODER HARDWARE TO PRE-PROCESS VIDEO CONTENT - Methods and systems may provide for invoking a plurality of parallel instances of a hardware video encoder, wherein the plurality of parallel instances includes a first encoder instance and a second encoder instance. Additionally, the first encoder instance may be used to make a scene change determination and a motion level determination with respect to the video content. In one example, the second encoder instance is used to encode the video content based on the scene change determination and the motion level determination. | 07-17-2014 |
20140270703 | EXPOSING MEDIA PROCESSING FEATURES - An apparatus and a system are described herein. The apparatus includes logic to render a video. The apparatus also includes logic to adjust a feature of a video in response to a power consumption, wherein the logic to adjust a feature of a video is integrated into an operating system of the apparatus. | 09-18-2014 |
20140270722 | MEDIA PLAYBACK WORKLOAD SCHEDULER - An apparatus, a computing device, a media playback workload scheduler, and a computer readable medium are described herein. The apparatus includes media playback workload scheduling logic to allocate a plurality of media frames for batch media processing, logic to process the media frames, and logic to render the processed media frames. | 09-18-2014 |
20140354667 | GPU ACCELERATED ADDRESS TRANSLATION FOR GRAPHICS VIRTUALIZATION - In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing GPU (Graphics Processing Unit) accelerated address translation for graphics virtualization. In one embodiment, such a system includes a main memory having a plurality of machine physical addresses; a graphics processor unit having graphics memory therein; an address translation service integrated with the graphics processor unit; a hypervisor to manage one or more guest machines; wherein the hypervisor is to configure a lookup table within the graphics memory of the graphics processor unit; and further wherein the address translation service of the graphics processor unit is to translate a guest physical address for one of the one or more guest machines to a corresponding machine physical address within the main memory. Such a graphics processor unit may be implemented separate from a system, for example, embodied within a silicon integrated circuit. | 12-04-2014 |