Liu, Pingzhen City
Dong-Yu Liu, Pingzhen City TW
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20130024689 | Method and System for Providing Secret-Less Application Framework - In one embodiment, providing, by a client device, device information and key data over a network to a server device, the device information uniquely identifying the client device; generating a device key, by a device key generation logic, at the server device based on the device information; receiving a module from the server device, the module comprising a bound content key and the device key generation logic, wherein the bound content key is encrypted by the device key at the server device; and processing protected content using the module. | 01-24-2013 |
20140280508 | Systems and Methods for Device Identity Delegation for Application Software - A method implemented in a delegating server for binding a device identity to a software application comprises receiving registration data from a client device executing a software application and assigning a device identifier to the client device and registering the client device with the delegating server based on the registration data. The method further comprises facilitating communication between the client device and the service provider based on the device identifier, wherein the delegating server is located between the client device and the service provider. | 09-18-2014 |
Heng-Kai Liu, Pingzhen City TW
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20130320555 | EDA TOOL AND METHOD, AND INTEGRATED CIRCUIT FORMED BY THE METHOD - A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N−1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks. | 12-05-2013 |
20130326447 | METHOD AND SYSTEM FOR LAYOUT PARASITIC ESTIMATION - A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances. | 12-05-2013 |
Steven Liu, Pingzhen City TW
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20140078478 | METHOD OF OPTIMIZING LITHOGRAPHY TOOLS UTILIZATION - A lithography cluster includes at least two lithography cells having a first lithography cell and a second lithography cell, an interface unit configured to integrate with the first lithography cell and the second lithography cell. The first lithography cell includes a first track and a first exposing tool and a second lithography cell includes a second track and a second exposing tool. The interface station includes a first interface buffer configured to couple the first track, a second interface buffer configured to couple the second track, a conveyor configured to couple the first interface buffer and the second interface buffer, and a robot configure to move along the conveyor, where in the robot transfers a substrate between functions of multiple functions within the first lithography cell, the second lithography cell, or between the first lithography cell and the second lithography cell. | 03-20-2014 |
Yen-Tzu Liu, Pingzhen City TW
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20120013603 | Depth Map Enhancing Method - The present invention discloses a depth map enhancing method. The method includes steps of obtaining an original depth map and a depth related parameter and storing the original depth map and the depth related parameter into a storage medium; quantifying the gray level of every pixel in the original depth map between 0 and 1 to obtain a plurality of quantified gray levels; raising the depth related parameter to the power of every quantified gray level respectively, subtracting 1, being divided by the value of the depth related parameter subtracting 1 and then being multiplied by a max gray level value to obtain a plurality of depth-relation-enhanced gray levels; and evenly distributing the plurality of depth-relation-enhanced gray levels between 0 and the max gray level value according to the relative proportional relationship among the plurality of depth-relation-enhanced gray levels to obtain a plurality of final gray levels. | 01-19-2012 |
Zhe-Ju Liu, Pingzhen City TW
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20130249040 | Structures for Grounding Metal Shields in Backside Illumination Image Sensor Chips - A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed on the front side of the semiconductor substrate. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the dielectric layer is over a back surface of the semiconductor substrate. A metal shield is over the dielectric layer and overlapping the photo-sensitive device. A metal plug penetrates through the dielectric layer, wherein the metal plug electrically couples the metal shield to the semiconductor substrate. | 09-26-2013 |
20140264687 | IMAGE SENSOR WITH TRENCHED FILLER GRID - Among other things, one or more image sensors and techniques for forming such image sensors are provided. An image sensor comprises a photodiode array configured to detect light. A filler grid is formed over the photodiode array, such as over a dielectric grid. The filler grid comprises one or more filler structures, such as a first filler structure that provides a light propagation path to a first photodiode that is primarily through the first filler structure. In this way, signal strength decay of light along the light propagation path before detection by the first photodiode is mitigated. The image sensor comprises a reflective layer that channels light towards corresponding photodiodes. For example, a first reflective layer portion guides light towards the first photodiode and away from a second photodiode. In this way, crosstalk, otherwise resulting from detection of light by incorrect photodiodes, is mitigated. | 09-18-2014 |
Zhen-U Liu, Pingzhen City TW
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20130219249 | METHOD FOR DETERMINING PARITY CHECK MATRIX UTILIZED IN FLASH MEMORY SYSTEM AND RELATED FLASH MEMORY SYSTEM THEREOF - A method for determining a parity check matrix utilized in a flash memory system is disclosed. The parity check matrix comprises M×N blocks. The method comprises generating a first set of candidate blocks as candidates of a first set of blocks of the M×N blocks; calculating a plurality of first estimated results corresponding to the first set of candidate blocks; determining content of a first block of the M×N blocks according to a best result of the first estimated results; generating a second set of candidate blocks as candidates of a second set of blocks of the M×N blocks; calculating a plurality of second estimated results corresponding to the second set of candidate blocks by considering the content of the first block; determining content a second block of the M×N blocks according to the second estimated results. | 08-22-2013 |