Patent application number | Description | Published |
20080304296 | DC-DC and DC-AC power conversion system - A galvanic isolated DC-DC and DC-AC power conversion system is coupled to a plurality of DC sources which are derived from a combination of a plurality of single-phase and three-phase AC-DC converters. The DC-DC and DC-AC power conversion system in one embodiment is configured to provide mixed type outputs (mixed frequency, e.g. DC with 50 or 60 Hz, with 400 Hz; mixed voltage levels). | 12-11-2008 |
20080304300 | Power conversion system with galvanically isolated high frequency link - A power conversion system has a three-phase AC input, where each AC input phase is linked to a string of cascaded single-phase AC-DC converters placed in series with a three-phase AC-DC converter. Each single-phase AC-DC converter in one embodiment includes a silicon carbide (SiC) pulse width modulated MOSFET H-bridge that placed in series with the three-phase AC-DC converter that includes a silicon (Si) SCR bridge. The single-phase AC-DC converters and the three-phase AC-DC converter together in one embodiment include a mixed silicon-carbide (SiC) and silicon (Si) device topology. | 12-11-2008 |
20090194772 | Method For Fabricating Silicon Carbide Vertical MOSFET Devices - A method of forming a vertical MOSFET device includes forming a first trench within a semiconductor layer of a first polarity, the first trench generally defining a well region of a second polarity opposite the first polarity; growing a first epitaxial well layer of the second polarity over the original semiconductor layer; growing a second epitaxial source contact layer of the first polarity over the well layer; forming a second trench through the source contact layer and at least a portion of the well layer; growing a third epitaxial layer of the second polarity over the source contact layer; and planarizing at least the first and second epitaxial layers so as to expose an upper surface of the original semiconductor layer, wherein a top surface of the third epitaxial layer is substantially coplanar with a top surface of the source contact layer prior to ohmic contact formation. | 08-06-2009 |
20100038058 | HEAT SINK AND COOLING AND PACKAGING STACK FOR PRESS-PACKAGES - A heat sink for directly cooling at least one electronic device package is provided. The electronic device package has an upper contact surface and a lower contact surface. The heat sink comprises a cooling piece formed of at least one thermally conductive material. The cooling piece defines multiple inlet manifolds configured to receive a coolant and multiple outlet manifolds configured to exhaust the coolant. The inlet and outlet manifolds are interleaved. The cooling piece further defines multiple millichannels configured to receive the coolant from the inlet manifolds and to deliver the coolant to the outlet manifolds. The millichannels and inlet and outlet manifolds are further configured to directly cool one of the upper and lower contact surface of the electronic device package by direct contact with the coolant, such that the heat sink comprises an integral heat sink. | 02-18-2010 |
20100038774 | ADVANCED AND INTEGRATED COOLING FOR PRESS-PACKAGES - A heat sink for cooling at least one electronic device package is provided. The electronic device package has an upper contact surface and a lower contact surface. The heat sink comprises at least one thermally conductive material and defines multiple inlet manifolds configured to receive a coolant, multiple outlet manifolds configured to exhaust the coolant, and multiple millichannels configured to receive the coolant from the inlet manifolds and to deliver the coolant to the outlet manifolds. The manifolds and millichannels are disposed proximate to the respective one of the upper and lower contact surface of the electronic device package for cooling the respective surface with the coolant. | 02-18-2010 |
20100157526 | Low cost anufacturing of micro-channel heatsink - A cooling device includes a ceramic substrate with a metal layer bonded to an outer planar surface. The cooling device also includes a channel layer bonded to an opposite side of the ceramic substrate and a manifold layer bonded to an outer surface of the channel layer. The substrate layers are bonded together using a high temperature process such as brazing to form a single substrate assembly. A plenum housing is bonded to the single substrate assembly via a low temperature bonding process such as adhesive bonding and is configured to provide extended manifold layer inlet and outlet ports. | 06-24-2010 |
20100226093 | METHODS FOR MAKING MILLICHANNEL SUBSTRATE, AND COOLING DEVICE AND APPARATUS USING THE SUBSTRATE - A substrate for power electronics mounted thereon, comprises a middle ceramic layer having a lower surface and an upper surface, an upper metal layer attached to the upper surface of the middle ceramic layer, and a lower metal layer attached to the lower surface of the middle ceramic layer. The lower metal layer has a plurality of millichannels configured to deliver a coolant for cooling the power electronics, wherein the millichannels are formed on the lower metal layer prior to attachment to the lower surface of the middle ceramic layer. Methods for making a cooling device and an apparatus are also presented. | 09-09-2010 |
20100302734 | HEATSINK AND METHOD OF FABRICATING SAME - A heatsink assembly for cooling a heated device includes a ceramic substrate having a plurality of cooling fluid channels integrated therein. The ceramic substrate includes a topside surface and a bottomside surface. A layer of electrically conducting material is bonded or brazed to only one of the topside and bottomside surfaces of the ceramic substrate. The electrically conducting material and the ceramic substrate have substantially identical coefficients of thermal expansion. | 12-02-2010 |
20110101515 | POWER MODULE ASSEMBLY WITH REDUCED INDUCTANCE - A device is provided that includes a first conductive substrate and a second conductive substrate. A first power semiconductor component having a first thickness can be electrically coupled to the first conductive substrate. A second power semiconductor component having a second thickness can be electrically coupled to the second conductive substrate. A positive terminal can also be electrically coupled to the first conductive substrate, while a negative terminal can be electrically coupled to the second power semiconductor component, and an output terminal may be electrically coupled to the first power semiconductor component and the second conductive substrate. The terminals, the power semiconductor components, and the conductive substrates may thereby be incorporated into a common circuit loop, and may together be configured such that a width of the circuit loop in at least one direction is defined by at least one of the first thickness or the second thickness. | 05-05-2011 |
20110133874 | MAGNETIC COMPONENTS AND METHODS FOR MAKING THE SAME - A method for making a magnetic component is provided. The method comprises providing a core with one or more ridges protruding from one or more surfaces of the core, depositing one or more electrically conductive materials on the core, and removing at least a portion of the one or more ridges to form one or more continuous conductors wound around the core. Each of the one or more continuous conductors defines at least one insulating gap. Further, a magnetic component and methods for making the magnetic component are also presented. | 06-09-2011 |
20130075878 | COAXIAL POWER MODULE - A power module includes at least one semiconductor die holding structure. Each die holding structure has a substantially cylindrical outer profile and a central axis. Each die holding structure is disposed within a common cylindrical EMI shield. A plurality of semiconductor devices are mounted to each die holding structure to form a substantially symmetric die mounting pattern respect to the central axis of the die holding structure. | 03-28-2013 |
20150034969 | METHOD AND SYSTEM FOR A SEMICONDUCTOR DEVICE WITH INTEGRATED TRANSIENT VOLTAGE SUPPRESSION - A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value. | 02-05-2015 |