Patent application number | Description | Published |
20080222390 | Low Noise Coding for Digital Data Interface - A digital data interface system comprises a data transmitter configured to transmit a data word across a plurality of data lines. The data word can comprise a plurality of digital data bits having a bit number order from a lowest bit number to a highest bit number with the lowest ordered bit numbers having higher noise content and the highest ordered bit numbers having higher harmonic content. The system also comprises an encoder configured to arrange the plurality of digital data bits as serialized data sets to be transmitted over each of the plurality of data lines by the data transmitter with consecutive data bits of at least one serialized data set being matched such that bits with the higher harmonic content are matched with bits of the higher noise content to substantially mitigate of at least one of the noise content and the harmonic content of the data word. | 09-11-2008 |
20090021283 | HIGH SPEED LATCHED COMPARATOR - An improved latched comparator, including a track mode circuit, a latch and a latch and track select circuit. The track mode circuit includes two transistors having their sources connected together, and their respective gates receiving a respective first and second input, and their drains connected to the power supply by respective resistors. The latch includes a further two transistors having their sources connected together, a gate of each connected to a drain of the other, and their drains connected to a respective one of the common connection node of the first transistor and the first resistor, and the second transistor and the second resistor. The latch and track select circuit includes a further transistor having an source connected to a current sink connected to ground, having a gate connected to receive a track signal and having a drain connected to the common connection node of the first and second transistors, and a still further transistor having a source connected to the current sink connected to ground, having a gate connected to receive a latch signal and having a drain connected to the common connection node of the third and fourth transistors. Bipolar embodiments are also included. | 01-22-2009 |
20090039923 | TRACK-AND-HOLD CIRCUIT WITH LOW DISTORTION - A track-and-hold circuit capable of tracking an analog input signal and holding a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. A first capacitor is provided, having a first terminal connected to a power supply terminal. Tracking circuitry operates when in an on state to apply through a resistor a tracking voltage to a second terminal of the first capacitor that corresponds to the voltage of the analog input signal, by applying the tracking voltage to a first terminal of the resistor, the second terminal of the resistor being connected to the second terminal of the first capacitor. A switch, responsive to the track signal and the hold signal, operates to switch the tracking circuitry to an on state in response to the track signal and to an off state in response to the hold signal, the time of change from the track signal to the hold signal comprising the sampling instant. A second capacitor is provided, having a first terminal connected to the first terminal of the resistor and having a second terminal connected to a power supply terminal. The second capacitor substantially reduces frequency-dependent harmonic distortion. | 02-12-2009 |
20090073016 | PIPELINED ANALOG-TO-DIGITAL CONVERTER - One embodiment of the present invention includes a pipelined analog-to-digital converter (ADC) comprising a plurality of pipeline stages. At least one of the plurality of pipeline stages comprises a feedback transistor-follower combination interconnected between a positive source voltage and a summation node and configured to set a voltage of the summation node approximately equal to a sample-and-hold voltage associated with a preceding one of the plurality of pipeline stages. The at least one of the plurality of pipeline stages also comprises a current mirror coupled to the feedback transistor-follower combination configured to provide a first current that is approximately equal to a second current that is associated with the feedback transistor-follower combination. The at least one of the plurality of pipeline stages further comprises an output resistor configured to set an output voltage of the respective at least one of the plurality of pipeline stages based on the first current. | 03-19-2009 |
20090219059 | TRACK-AND-HOLD CIRCUIT WITH LOW DISTORTION - A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit. The RC network receives the analog input signal and is scaled to change the location of a zero to reduce the signal-dependence of the sampling instant. | 09-03-2009 |
20090219060 | METHOD AND APPARATUS OF SFDR ENHANCEMENT - A track-and-hold or sample-and-hold (S/H) circuit for an analog-to-digital converter (ADC) is provided. A difference between the disclosed S/H circuit and conventional S/H circuits is the use of a peaking circuit. This peaking circuit generally provides increased current to switching transistor when transitioning between track and hold which can increase the Spurious-Free Dynamic Range (SFDR) as low frequencies, by as much as 15 dB. | 09-03-2009 |
20100213986 | CLOCK BUFFER - An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage. Additionally, the first and second clamps is coupled to the collectors of the first, second, third, and fourth BJTs. | 08-26-2010 |
20100214144 | ERROR CORRECTION METHOD AND APPARATUS - A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output impedance. Included with the switched current source is an error correction transistor and a resistor that cooperate to feed a current back through a bias transistor to correct an error that generally results from the current gains or β's of transistors within the switched current source. To accomplish this, however, the resistor is selected to have a value that is sufficiently large such that current from the error correction transistor flows back through the bias transistor. | 08-26-2010 |
20110101955 | SYSTEM AND METHOD FOR IMPLEMENTING LOW-COST ELECTRONIC GYROSCOPES AND ACCELEROMETER - Accelerometers have a number of wide-ranging uses, and it is desirable to both increase their accuracy while decreasing size. Here, millimeter or sub-millimeter wavelength accelerometers are provided which has the advantage of having the high accuracy of an optical accelerometer, while being compact. Additionally, because millimeter or sub-millimeter wavelength signals are employed, cumbersome and awkward on-chip optical devices and bulky optical mediums can be avoided. | 05-05-2011 |
20110121868 | CLOCK BUFFER - An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage. Additionally, the first and second clamps is coupled to the collectors of the first, second, third, and fourth BJTs. | 05-26-2011 |
20110199972 | Wireless Chip-to-Chip Switching - Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. A router or switch receives data packets at input port ASICs. A routing table on the input port ASIC or on a routing ASIC is used to identify a destination port ASIC based upon header information in the data packet. The data packet is transmitted from the input port ASIC to the destination port ASIC using millimeter wave signals that are transmitted across a waveguide or a wireless interface. | 08-18-2011 |
20120044004 | TRACK AND HOLD ARCHITECTURE WITH TUNABLE BANDWIDTH - To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths. | 02-23-2012 |
20120068890 | HIGH SPEED DIGITAL INTERCONNECT AND METHOD - In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth. | 03-22-2012 |
20120068891 | CHIP TO DIELECTRIC WAVEGUIDE INTERFACE FOR SUB-MILLIMETER WAVE COMMUNICATIONS LINK - In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth. | 03-22-2012 |
20120086589 | PIPELINED CONTINUOUS-TIME SIGMA DELTA MODULATOR - Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise. | 04-12-2012 |
20120092199 | PIPELINED ADC HAVING A THREE-LEVEL DAC ELEMENTS - In conventional pipelined analog-to-digital converters (ADCs), it is common to employ digital-to-analog converters (DACs) in the ADC stages that use two-state switches or segments. A problem with this arrangement is that for each DAC state there is a noise contribution from each DAC switch, resulting from its current source. Here, however, a DAC is employed that uses three-state DAC switches, which reduces the noise contributions from the DAC switches' current sources and reduces the amount of area used. | 04-19-2012 |
20120098572 | LATCHED COMPARATOR HAVING ISOLATION INDUCTORS - Traditionally, latched comparators have suffered from performance problems related to exposure of the latch to load capacitances. Even attempts to isolate the latch from the load capacitances by way of resistors has resulted in performance problems (namely, voltage swing degradation). Here, however, a latched comparator is provided that employs inductors to generally provide isolation from load capacitances, which generally improves performance. Moreover, the latch has been modified to accommodate the inductors during a track period (namely, provision of grounding paths). | 04-26-2012 |
20120106211 | POWER FACTOR AND LINE DISTORTION METHOD AND APPARATUS - Today, power distribution systems can be used to supply power to many loads, and since many loads, such as servers, are reactive (i.e., have capacitors and/or inductors), line distortion and power factor can be an issue. Conventional techniques to correct for line distortion and power factor use a specialized circuit that is generally in series with the load, but these specialized circuits can be prohibitively expensive when used in large numbers. Here, however, a corrective power supply has been provided, which can correct for other parallel power supplies that can reduce cost. | 05-03-2012 |
20120286981 | COMPRESSIVE SENSING ANALOG-TO-DIGITAL CONVERTERS - Compressive sensing is an emerging field that attempts to prevent the losses associated with data compression and improve efficiency overall, and compressive sensing looks to perform the compression before or during capture, before energy is wasted. Here, several analog-to-digital converter (ADC) architectures are provided to perform compressive sensing. Each of these new architectures selects resolutions for each sample substantially at random and adjusts the sampling rate as a function of these selected resolutions. | 11-15-2012 |
20120306475 | SYSTEM AND METHOD FOR IMPLEMENTING LOW-COST ELECTRONIC GYROSCOPES AND ACCELEROMETER - Accelerometers have a number of wide-ranging uses, and it is desirable to both increase their accuracy while decreasing size. Here, millimeter or sub-millimeter wavelength accelerometers are provided which has the advantage of having the high accuracy of an optical accelerometer, while being compact. Additionally, because millimeter or sub-millimeter wavelength signals are employed, cumbersome and awkward on-chip optical devices and bulky optical mediums can be avoided. | 12-06-2012 |
20120326906 | PIPELINED CONTINUOUS-TIME SIGMA DELTA MODULATOR - Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise. | 12-27-2012 |
20130015990 | TRACK AND HOLD ARCHITECTURE WITH TUNABLE BANDWIDTH - To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths. | 01-17-2013 |
20130038480 | TRACK-AND-HOLD CIRCUIT WITH LOW DISTORTION - A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit. The RC network receives the analog input signal and is scaled to change the location of a zero to reduce the signal-dependence of the sampling instant. | 02-14-2013 |
20130063210 | HIGH SPEED AMPLIFIER - For high speed amplifiers, the parasitic capacitances from the differential input pair introduce a zero that can affect performance. Here, a neutralization network has been provided that compensates for this zero by shifting its position. This is generally accomplished by using a pair of capacitors that are cross-coupled across the differential input pair of the amplifier. | 03-14-2013 |
20130063291 | EXCESS LOOP DELAY COMPENSATION FOR A CONTINUOUS TIME SIGMA DELTA MODULATOR - A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined. | 03-14-2013 |
20130100551 | METHOD AND APPARATUS FOR REFLECTION CANCELLATION - A method for calibrating a reflection compensator is provided. A delay is initially set to a predetermined minimum, and an input pulse is transmitted across a transmission line. A compensation current is then applied after the delay. The reflection from the transmission line is digitized to generate a measurement, and a determination is made as to whether the compensation current substantially compensates for the reflection. If the compensation current does not substantially compensate for the reflection, then the delay is adjusted, and the process is repeated until the compensation current substantially compensates for the reflection. | 04-25-2013 |
20130146887 | DIODE FOR USE IN A SWITCHED MODE POWER SUPPLY - A tunable depletion diode is provided. Within this depletion diode, there is a depletion mode transistor that is coupled to the anode terminal at its gate and the cathode terminal at its drain. A diode is coupled between the source of the depletion mode transistor and the anode terminal, and a variable capacitor is coupled between the source of the depletion mode transistor and the anode terminal, where the capacitance of the variable capacitor is controls the reverse recovery time of the tunable depletion diode. | 06-13-2013 |
20130154483 | METHOD AND APPARATUS TO MEASURE LIGHT INTENSITY - A method for controlling a light emitting diode (LED) is provided. Initially, the LED, which had been active, is deactivated, and a voltage for a current that corresponds to the persistence of the LED is generated. The voltage is then integrated so as to generate an integrated voltage, and the integrated voltage is compared to a threshold. When the integrated voltage is less than the threshold, the LED is then activated. | 06-20-2013 |
20130258892 | Wireless Chip-to-Chip Switching - Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. A router or switch receives data packets at input port ASICs. A routing table on the input port ASIC or on a routing ASIC is used to identify a destination port ASIC based upon header information in the data packet. The data packet is transmitted from the input port ASIC to the destination port ASIC using millimeter wave signals that are transmitted across a waveguide or a wireless interface. | 10-03-2013 |
20130262036 | Sensor Power Management - A sensor power management arrangement includes a signal processing circuit configured to receive signal from a sensor, to test the signal against at least one criterion, and to pass the signal for further processing in response to the signal passing the at least one criterion. In this way, only signals that are of a sufficient importance or significance will consume the maximum amount of processing energy and through processing by later processes or circuitry. Should a signal from a sensor not be strong enough or meet other criteria, power will not be wasted in preparing that signal for provision to the microcontroller or microprocessor. Additional flexibility in the sensor power management can be realized by adjusting the criteria against which the sensor signal is compared based on a status of the sensor apparatus. | 10-03-2013 |
20130265732 | INTERCHIP COMMUNICATION USING A DIELECTRIC WAVEGUIDE - An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide. | 10-10-2013 |
20130265733 | INTERCHIP COMMUNICATION USING AN EMBEDDED DIELECTRIC WAVEGUIDE - An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide. | 10-10-2013 |
20130265734 | INTERCHIP COMMUNICATION USING EMBEDDED DIELECTRIC AND METAL WAVEGUIDES - An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide. | 10-10-2013 |