Patent application number | Description | Published |
20080198743 | DATA FLOW CONTROL FOR SIMULTANEOUS PACKET RECEPTION - Embodiments of the present invention provide methods, a module, and a system for calculating a credit limit for an interface capable of receiving multiple packets simultaneously. Generally, the multiple packets are simultaneously received at an interface on the second device, each packet being one of a plurality of packet types, and a flow control credit limit to be transmitted to the first device is adjusted based on the combination of packet types of the simultaneously received packets. | 08-21-2008 |
20100023568 | Dynamic Range Adjusting Floating Point Execution Unit - A floating point execution unit is capable of selectively repurposing a subset of the significand bits in a floating point value for use as additional exponent bits to dynamically provide an extended range for floating point calculations. A significand field of a floating point operand may be considered to include first and second portions, with the first portion capable of being concatenated with the second portion to represent the significand for a floating point value, or, to provide an extended range, being concatenated with the exponent field of the floating point operand to represent the exponent for a floating point value. | 01-28-2010 |
20100042812 | Data Dependent Instruction Decode - A circuit arrangement and method support data dependent instruction decoding, whereby instructions are decoded, in part, using decode data that is stored in operand registers identified by such instructions. An instruction may include an opcode and at least one operand that identifies a register. During execution of the instruction, the instruction is first decoded using the opcode, and then decode data stored in the operand register is retrieved and used to further decode the instruction, e.g., to select from among a plurality of operations or instruction types associated with the same opcode. | 02-18-2010 |
20100042813 | Redundant Execution of Instructions in Multistage Execution Pipeline During Unused Execution Cycles - A pipelined execution unit uses the bubbles that occur during execution to selectively repeat operations performed in one or more stages of a multistage execution pipeline to verify the results of such operations during otherwise unused execution cycles for the execution pipeline. Whenever a bubble follows a particular instruction within an execution pipeline, the result of an operation that is performed for that instruction by a particular stage of the execution pipeline may be stored, and the operation may be repeated by the stage in a subsequent execution cycle in which no productive operation would otherwise be performed due to the presence of the bubble. The results of the operations may then be compared and used to either verify the original result or identify a potential error in the execution of the instruction. | 02-18-2010 |
20100125722 | Multithreaded Processing Unit With Thread Pair Context Caching - A circuit arrangement and method utilize thread pair context caching, where a pair of hardware threads in a multithreaded processor, which are each capable of executing a process, are effectively paired together, at least temporarily, to perform context switching operations such as context save and/or load operations in advance of context switches performed in one or more of such paired hardware threads. By doing so, the overall latency of a context switch, where both the context for a process being switched from must be saved, and the context for the process being switched to must be loaded, may be reduced. | 05-20-2010 |
20110298788 | PERFORMING VECTOR MULTIPLICATION - A method includes receiving packed data corresponding to pixel components to be processed at a graphics pipeline. The method includes unpacking the packed data to generate floating point numbers that correspond to the pixel components. The method also includes routing each of the floating point numbers to a separate lane of the graphics pipeline. Each of the floating point numbers are to be processed by multiplier units of the graphics pipeline. | 12-08-2011 |
20110302450 | FAULT TOLERANT STABILITY CRITICAL EXECUTION CHECKING USING REDUNDANT EXECUTION PIPELINES - A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the results of the multiple instances of the instructions can be compared for the purpose of detecting errors. For other types of instructions for which fault tolerant or stability critical execution is not required or desired, the redundant execution pipelines are utilized in a more conventional manner, enabling multiple non-stability critical instructions to be concurrently issued to and executed by the redundant execution pipelines. As such, for non-stability critical program code, the performance benefits of having multiple redundant execution units are preserved, yet in the instances where fault tolerant or stability critical execution is desired for certain program code, the redundant execution units may be repurposed to provide greater assurances as to the fault-free execution of such instructions. | 12-08-2011 |
20110321049 | Programmable Integrated Processor Blocks - An integrated processor block of the network on a chip is programmable to perform a first function. The integrated processor block includes an inbox to receive incoming packets from other integrated processor blocks of a network on a chip, an outbox to send outgoing packets to the other integrated processor blocks, an on-chip memory, and a memory management unit to enable access to the on-chip memory. | 12-29-2011 |
20120084535 | Opcode Space Minimizing Architecture Utilizing Instruction Address to Indicate Upper Address Bits - Due to the ever expanding number of registers and new instructions in modern microprocessor cores, the address widths present in the instruction encoding continue to widen, and fewer instruction opcodes are available, making it more difficult to add new instructions to existing architectures without resorting to inelegant tricks that have drawbacks such as source destructive operations. The disclosed invention utilizes specialized decode and address calculation hardware that concatenates a fixed number of least significant bits of the instruction address onto the upper address bits of each register address portion contained in the instruction, yielding the full register address, instead of providing the full register address widths for every register used in the instruction. This frees up valuable opcode space for other instructions and avoids compiler complexity. This aligns nicely with how most loops are unrolled in assembly language, where independent operations are near each other in memory. | 04-05-2012 |
20130036296 | FLOATING POINT EXECUTION UNIT WITH FIXED POINT FUNCTIONALITY - A floating point execution unit is capable of selectively repurposing one or more adders in an exponent path of the floating point execution unit to perform fixed point addition operations, thereby providing fixed point functionality in the floating point execution unit. | 02-07-2013 |
20130111186 | INSTRUCTION ADDRESS ADJUSTMENT IN RESPONSE TO LOGICALLY NON-SIGNIFICANT OPERATIONS | 05-02-2013 |
20130138925 | PROCESSING CORE WITH SPECULATIVE REGISTER PREPROCESSING - A method and circuit arrangement speculatively preprocess data stored in a register file during otherwise unused cycles in an execution unit, e.g., to prenormalize denormal floating point values stored in a floating point register file, to decompress compressed values stored in a register file, to decrypt encrypted values stored in a register file, or to otherwise preprocess data that is stored in an unprocessed form in a register file. | 05-30-2013 |
20130159591 | VERIFYING DATA RECEIVED OUT-OF-ORDER FROM A BUS - In an embodiment, load transactions are issued to a bus. The load transactions are stalled if the bus cannot accept additional load transactions, and the load transactions are restarted after the bus can accept the additional load transactions. Responses are received from the bus to the load transactions out-of-order from an order that the load transactions were sent to the bus. The responses comprise data and index values that indicate an order that the load transactions were received by the bus. The data is compared in the order that the load transactions were received by the bus against expected data in the order that the load transaction were sent to the bus. | 06-20-2013 |
20130159683 | INSTRUCTION PREDICATION USING INSTRUCTION ADDRESS PATTERN MATCHING - A particular method includes receiving, at a processor, an instruction and an address of the instruction. The method also includes preventing execution of the instruction based at least in part on determining that the address is within a range of addresses. | 06-20-2013 |
20130185477 | VARIABLE LATENCY MEMORY DELAY IMPLEMENTATION - A method includes receiving, from a processor, a first read request mapped including a first read request address to a first memory location of a register array and a second read request including a second read request address to a second memory location of a register array. The method includes assigning a first simulated time delay to the first read request and assigning a second simulated time delay to the second read request. The method includes, in response to a first elapsed time being equal to the first simulated time delay, outputting a first read request response including first data. The first elapsed time commences upon receipt of the first read request. The method includes, in response to a second elapsed time being equal to the second simulated time delay, outputting a second read request response including second data. The second elapsed time commences upon receipt of the second read request. | 07-18-2013 |
20130185604 | FAULT TOLERANT STABILITY CRITICAL EXECUTION CHECKING USING REDUNDANT EXECUTION PIPELINES - A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the results of the multiple instances of the instructions can be compared for the purpose of detecting errors. For other types of instructions for which fault tolerant or stability critical execution is not required or desired, the redundant execution pipelines are utilized in a more conventional manner, enabling multiple non-stability critical instructions to be concurrently issued to and executed by the redundant execution pipelines. As such, for non-stability critical program code, the performance benefits of having multiple redundant execution units are preserved, yet in the instances where fault tolerant or stability critical execution is desired for certain program code, the redundant execution units may be repurposed to provide greater assurances as to the fault-free execution of such instructions. | 07-18-2013 |
20130191432 | DYNAMIC RANGE ADJUSTING FLOATING POINT EXECUTION UNIT - A floating point execution unit is capable of selectively repurposing a subset of the significand bits in a floating point value for use as additional exponent bits to dynamically provide an extended range for floating point calculations. A significand field of a floating point operand may be considered to include first and second portions, with the first portion capable of being concatenated with the second portion to represent the significand for a floating point value, or, to provide an extended range, being concatenated with the exponent field of the floating point operand to represent the exponent for a floating point value. | 07-25-2013 |