Patent application number | Description | Published |
20090202069 | METHOD AND SYSTEM FOR GENERATING A SECURE KEY - A method, system on a chip, and computer system for generating more robust keys which utilize data occupying relatively small die areas is disclosed. Embodiments provide a convenient and effective mechanism for generating a key for use in securing data on a portable electronic device, where the key is generated from repurposed data and a relatively small amount. A multi-stage encryption algorithm may be performed to generate the key, where the first stage may include encrypting the secure data, and the second stage may include encrypting the result of a logical operation on the encrypted secure data with a unique identifier of the portable electronic device. A secret key may be used as the encryption key for each stage. The result of the second encryption stage may include the generated key which may be used to perform subsequent operations on the portable electronic device. | 08-13-2009 |
20100146218 | System And Method For Maintaining Cache Coherency Across A Serial Interface Bus - A method for executing processing operations using data stored in a memory. The method includes generating a snoop request configured to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on a bus, and a cache line address identifying where in the data cache the second data is located. The method further includes causing the snoop request to be transmitted over the bus to the second processor, extracting the cache line address from the snoop request, determining whether the second data is coherent, generating a complete message that includes completion information indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor. | 06-10-2010 |
20100146222 | Chipset Support For Non-Uniform Memory Access Among Heterogeneous Processing Units - A method for providing a first processor access to a memory associated with a second processor. The method includes receiving a first address map from the first processor that includes an MMIO aperture for a NUMA device, receiving a second address map from a second processor that includes MMIO apertures for hardware devices that the second processor is configured to access, and generating a global address map by combining the first and second address maps. The method further includes receiving an access request transmitted from the first processor to the NUMA device, generating a memory access request based on the first access request and a translation table that maps a first address associated with the first access request into a second address associated with the memory associated with the second processor, and routing the memory access request to the memory based on the global address map. | 06-10-2010 |
20100146620 | Centralized Device Virtualization Layer For Heterogeneous Processing Units - A method for providing an operating system access to devices, including enumerating hardware devices and virtualized devices, where resources associated with a first hardware device are divided into guest physical resources creating a software virtualized device, and multiple instances of resources associated with a second hardware device are advertised thereby creating a hardware virtualized device. First and second permission lists are generated that specify which operating systems are permitted to access the software virtualized device and the hardware virtualized device, respectively. First and second sets of virtual address maps are generated, where each set maps an address space associated with either the software virtualized device or the hardware virtualized device into an address space associated with each operating system included in the corresponding permission list. The method further includes arbitrating access requests from each of the plurality of operating systems based on the permission lists and the virtual address maps. | 06-10-2010 |
20120290796 | SYSTEM AND METHOD FOR MAINTAINING CACHE COHERENCY ACROSS A SERIAL INTERFACE BUS USING A SNOOP REQUEST AND COMPLETE MESSAGE - Techniques are disclosed for maintaining cache coherency across a serial interface bus such as a Peripheral Component Interconnect Express (PCIe) bus. The techniques include generating a snoop request (SNP) to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on the serial interface bus and causing the snoop request to be transmitted over the serial interface bus to a second processor. The techniques further include extracting a cache line address from the snoop request, determining whether the second data is coherent, generating a complete message (CPL) indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor. The snoop request and complete messages may be vendor defined messages. | 11-15-2012 |
20120304285 | CENTRALIZED DEVICE VIRTUALIZATION LAYER FOR HETEROGENEOUS PROCESSING UNITS - A method for providing an operating system access to devices, including enumerating hardware devices and virtualized devices, where resources associated with a first hardware device are divided into guest physical resources creating a software virtualized device, and multiple instances of resources associated with a second hardware device are advertised thereby creating a hardware virtualized device. First and second permission lists are generated that specify which operating systems are permitted to access the software virtualized device and the hardware virtualized device, respectively. First and second sets of virtual address maps are generated, where each set maps an address space associated with either the software virtualized device or the hardware virtualized device into an address space associated with each operating system included in the corresponding permission list. The method further includes arbitrating access requests from each of the plurality of operating systems based on the permission lists and the virtual address maps. | 11-29-2012 |
20140104450 | SYSTEM AND METHOD FOR OPTIMIZING IMAGE QUALITY IN A DIGITAL CAMERA - A digital camera includes an image optimization engine configured to generate an optimized image based on a raw image captured by the digital camera. The image optimization engine implements one or more machine learning engines in order to select rendering algorithms and rendering algorithm arguments that may then be used to render the raw image. | 04-17-2014 |
20140152848 | TECHNIQUE FOR CONFIGURING A DIGITAL CAMERA - A camera tuning engine within a digital camera includes a machine learning engine that generates a configuration file for the digital camera based on raw images captured by the digital camera. The digital camera implements a set of rendering algorithms that render trial images from the raw images based on parameters included in the configuration file. A training engine within the camera tuning engine then compares the trial images to target images provided from an external source. Based on differences between the trial images and the target images, the training engine adjusts weight values within the machine learning engine. By performing this process iteratively, the training engine trains the machine learning engine to generate a configuration file that may be used by the digital camera to render images that are similar to the target images. | 06-05-2014 |