Patent application number | Description | Published |
20080316662 | Reducing input capacitance for high speed integrated circuits - An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity if formed underneath the pad. Other embodiments are described and claimed. | 12-25-2008 |
20100149858 | Providing a Ready-Busy Signal From a Non-Volatile Memory Device to a Memory Controller - A common standard may be used for both dynamic random access memories and non-volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package connector on the non-volatile memory may be used for one function that does not involve communications with the memory controller during reading and may be used for communications with the memory controller during writing. Particularly, those communications during writing may be to indicate to the memory controller when the memory is ready for writing and when the memory is busy so that a write must be deferred until the memory is ready to be written to. | 06-17-2010 |
20100291867 | WIRELESS INTERFACE TO PROGRAM PHASE-CHANGE MEMORIES - A Phase-Change Memory (PCM) coupled to receive power provided by near-field coupling to operate the PCM and receive factory programming data entered through the antenna for storage in the PCM. | 11-18-2010 |
20110040909 | HIGH-SPEED WIRELESS SERIAL COMMUNICATION LINK FOR A STACKED DEVICE CONFIGURATION USING NEAR FIELD COUPLING - A memory module houses stacked memory devices and a memory controller each having a near-field interface coupled to loop antennas to communicate over-the-air data. A coil is formed on a memory device substrate or molded into a plastic mold to create near-field magnetic coupling with the stacked memory devices and the memory controller. | 02-17-2011 |
20110307653 | CACHE COHERENCE PROTOCOL FOR PERSISTENT MEMORIES - Subject matter disclosed herein relates to cache coherence of a processor system that includes persistent memory. | 12-15-2011 |
20110307665 | PERSISTENT MEMORY FOR PROCESSOR MAIN MEMORY - Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory. | 12-15-2011 |
20120039118 | Providing a Ready-Busy Signal From a Non-Volatile Memory Device to a Memory Controller - A common standard may be used for both dynamic random access memories and non-volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package connector on the non-volatile memory may be used for one function that does not involve communications with the memory controller during reading and may be used for communications with the memory controller during writing. Particularly, those communications during writing may be to indicate to the memory controller when the memory is ready for writing and when the memory is busy so that a write must be deferred until the memory is ready to be written to. | 02-16-2012 |
20130003474 | PROVIDING A READY-BUSY SIGNAL FROM A NON-VOLATILE MEMORY DEVICE TO A MEMORY CONTROLLER - A common standard may be used for both dynamic random access memories and non volatile memories, despite the fact that the non-volatile memory generally needs bidirectional communications to coordinate writing with a memory controller. In one embodiment, a package connector on the non-volatile memory may be used for one function that does not involve communications with the memory controller during reading and may be used for communications with the memory controller during writing. Particularly, those communications during writing may be to indicate to the memory controller when the memory is ready for writing and when the memory is busy so that a write must be deferred until the memory is ready to be written to. | 01-03-2013 |
20130031315 | MULTI-DEVICE MEMORY SERIAL ARCHITECTURE - Subject matter disclosed herein relates to memory devices comprising a memory array, a first port to interface with a memory controller directly or indirectly via another memory device, a second port to interface with yet another memory device, and a switch to selectively electrically connect the memory controller to a circuit path leading to the second port or to the memory array, wherein the switch may be responsive to a signal generated by the memory controller. | 01-31-2013 |
20140009218 | SUPPLY VOLTAGE OR GROUND CONNECTIONS INCLUDING BOND PAD INTERCONNECTS FOR INTEGRATED CIRCUIT DEVICE - Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond pads on an integrated circuit die may be connected together via one or more electrically conductive interconnects. | 01-09-2014 |
20140015133 | SUPPLY VOLTAGE OR GROUND CONNECTIONS FOR INTEGRATED CIRCUIT DEVICE - Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond fingers may be connected together via one or more electrically conductive interconnects. | 01-16-2014 |
20140223103 | PERSISTENT MEMORY FOR PROCESSOR MAIN MEMORY - Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory. | 08-07-2014 |