Patent application number | Description | Published |
20140240335 | CACHE ALLOCATION IN A COMPUTERIZED SYSTEM - System and method for operating a solid state memory containing a memory space. The present invention provides a computerized system that includes a solid state memory having a memory space; a controller adapted to use a first portion of the memory space as a cache; and a garbage collector adapted to use a second portion of the memory space to collect garbage in the solid state memory. The controller is adapted to change a size of at least one of the first portion and the second portion of the memory space during operation of the solid state memory. | 08-28-2014 |
20140359228 | CACHE ALLOCATION IN A COMPUTERIZED SYSTEM - A computerized system comprises a solid state memory and a controller adapted to use the solid state memory as a cache for the computerized system. The controller is adapted to add or to remove a chunk of data from the cache based on a detected frequency of occurrence of the chunk of data in the computerized system. | 12-04-2014 |
20150067294 | METHOD AND SYSTEM FOR ALLOCATING A RESOURCE OF A STORAGE DEVICE TO A STORAGE OPTIMIZATION OPERATION - Allocating a resource of a storage device to a storage optimization operation. An available resource of the storage device is monitored. Determining an allocation proportion of the resource allocated to the storage optimization operation, based on at least one of historical running information and a predicted value of a performance improvement caused by the storage optimization operation. Allocating the resource of the storage device to the storage optimization operation based on the available resource and the allocation proportion. | 03-05-2015 |
20160092352 | REDUCING WRITE AMPLIFICATION IN SOLID-STATE DRIVES BY SEPARATING ALLOCATION OF RELOCATE WRITES FROM USER WRITES - In one embodiment, a method includes maintaining a first open logical erase block for user writes, maintaining a second open logical erase block for relocate writes, wherein the first and second open logical erase blocks are different logical erase blocks, receiving a first data stream having the user writes, transferring the first data stream to the first open logical erase block, receiving a second data stream having the relocate writes, and transferring the second data stream to the second open logical erase block. Other systems, methods, and computer program products are described in additional embodiments. | 03-31-2016 |
20160110124 | DETECTING ERROR COUNT DEVIATIONS FOR NON-VOLATILE MEMORY BLOCKS FOR ADVANCED NON-VOLATILE MEMORY BLOCK MANAGEMENT - Non-volatile memory block management. A method according to one embodiment includes determining a block health of at least some non-volatile memory blocks of a plurality of non-volatile memory blocks that are configured to store data. An error count margin threshold is calculated for each of the at least some non-volatile memory blocks. A determination is made as to whether the error count margin threshold of any of the at least some non-volatile memory blocks has been exceeded. A memory block management function is triggered upon determining that the error count margin threshold of any of the non-volatile memory blocks has been exceeded. | 04-21-2016 |
20160110248 | STORAGE ARRAY MANAGEMENT EMPLOYING A MERGED BACKGROUND MANAGEMENT PROCESS - In at least one embodiment, a controller of a non-volatile memory array iteratively performs a merged background management process independently of any host system's demand requests targeting the memory array. During an iteration of the merged background management process, the controller performs a read sweep by reading data from each of a plurality of page groups within the memory array and recording page group error statistics regarding errors detected by the reading for each page group, where each page group is formed of a respective set of one or more physical pages of storage in the memory array. During the iteration of the merged background management process, the controller employs the page group error statistics recorded during the read sweep in another background management function. | 04-21-2016 |
20160132392 | NON-VOLATILE MEMORY DATA STORAGE WITH LOW READ AMPLICATION - In one embodiment, an apparatus includes one or more memory devices, each memory device having non-volatile memory configured to store data, and a memory controller connected to the one or more memory devices, the memory controller being configured to receive data to be stored to the one or more memory devices, store read-hot data within one error correction code (ECC) codeword as aligned data, and store read-cold data to straddle two or more ECC codewords as non-aligned data and/or dispersed data. According to another embodiment, a method for storing data to non-volatile memory includes receiving data to store to one or more memory devices, each memory device including non-volatile memory configured to store data, storing read-hot data within one ECC codeword as aligned data, and storing read-cold data to straddle two or more ECC codewords as non-aligned data and/or dispersed data. | 05-12-2016 |
20160141048 | BACKGROUND THRESHOLD VOLTAGE SHIFTING USING BASE AND DELTA THRESHOLD VOLTAGE SHIFT VALUES IN NON-VOLATILE MEMORY - In one embodiment, a computer-implemented method includes determining, by a processor, after the writing of data to a non-volatile memory block, one or more delta threshold voltage shift (TVS | 05-19-2016 |