Patent application number | Description | Published |
20110062983 | REDUCING SWITCHING NOISE - Described herein are various principles for operating a transmitter circuit to reduce noise affecting a signal being generated and reducing jitter. In some embodiments, a circuit is operated in a way that switching occurs at or above a bit rate of transmission, such that at least one switch changes state at least for every bit. Operating the circuit in such a way leads to a switching rate that is above a resonant frequency of the circuit and prevents large oscillations and noise from being inserted into the signal and causing communication problems. | 03-17-2011 |
20110090002 | HIGH VOLTAGE TOLERANCE OF EXTERNAL PAD CONNECTED MOS IN POWER-OFF MODE - An integrated circuit includes a number of pads. The integrated circuit further includes a cascode transistor having an open drain connection to a first one of the pads. A bias generator circuit is included in the integrated circuit. The bias generator circuit has an output connected to a gate terminal of the cascode transistor. In a first mode of operation, the bias generator outputs a bias signal that is derived from an integrated circuit supply voltage present at a second one of the pads. However, in a second mode of operation provided when the integrated circuit supply voltage is not present, the bias generator generates the bias signal derived from a voltage present at the first one of the pads. | 04-21-2011 |
20110273215 | HIGH JITTER AND FREQUENCY DRIFT TOLERANT CLOCK DATA RECOVERY - In a method for recovery of a clock from a received digital data stream and an apparatus for recovering a clock from a received digital data stream, phase-shifted clock signals are generated from a receiver's clock. After selecting one of the phase-shifted clock signals, two other phase-shifted clock signals are determined. Depending on sample values taken at rising/falling edges of the three selected phase-shifted clock signals, counter values are increased and compared. The selection of phase-shifted clock signals and the steps of sampling the input digital data stream, comparing the values and increasing counter values, if required, are repeatedly performed until the comparison result of the counter values indicates that one of the latter determined phase-shifted clock signals strobes the received digital data stream in the centre of a bit period. | 11-10-2011 |
20120169403 | POWER HARVESTING IN OPEN DRAIN TRANSMITTERS - A transmitter having at least one channel comprising a first differential circuit driven by a differential data signal, the first differential circuit configured to output the differential data at a first and second output and a first control circuit coupled between the first differential circuit and the first and second output, the first control circuit driven by a drive voltage. | 07-05-2012 |
20120169410 | TECHNIQUE TO MINIMIZE VDS MISMATCH DRIVEN VOLTAGE SWING VARIATION IN OPEN DRAIN TRANSMITTER - A switching circuit includes a source follower current mirror having an input, an output, a first source terminal, a bias terminal, and a second source terminal; a current source coupled to the input of the current mirror; an output terminal coupled to the output of the current mirror; a first bias transistor coupled to the first source terminal; a second bias transistor coupled to bias terminal of the current mirror; and a driver transistor coupled to the second source terminal. An input transistor in the current mirror is sized such that the input voltage is substantially independent of the supply voltage. | 07-05-2012 |
20120169438 | HDMI RECEIVER - An embodiment of a transmitter includes an amplifier having first and second differential output nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential output node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential output node and having a second node coupled to the supply node. An embodiment of a receiver includes an amplifier having first and second differential input nodes, a first supply node, a first pull-up impedance having a first node coupled to the first differential input node and having a second node coupled to the supply node, and a second pull-up impedance having a first node coupled to the second differential input node and having a second node coupled to the supply node. In an embodiment, the transmitter and receiver are capacitively coupled to one another. | 07-05-2012 |
20120297028 | INTEGRATED REMOTE POLLUTION MONITORING AND INDEXING SYSTEM AND METHOD THEREOF - The invention relates to a system for integrated remote monitoring and measuring of real time pollution levels together with real time weather details and a method of aggregating, analyzing and indexing the disparate data into a single measurable and accessible real time data for the user. The invention further relates to a method and means of displaying the pollution index of different types of pollution levels of air, water, sewage, noise, radiation, light and soil and weather details in real time through various displaying methods. | 11-22-2012 |
20140368281 | MID-BAND PSRR CIRCUIT FOR VOLTAGE CONTROLLED OSCILLATORS IN PHASE LOCK LOOP - A circuit generates a compensation signal that can remove noise in a VCO introduced by a supply signal (i.e., supply-side noise). The circuit includes two transistors connected in series. A resistor is connected between the gate of the first transistor and the supply signal, and a capacitor is connected between the gate of the second transistor and the supply signal. The circuit is designed so that the transconductance of one transistor is greater than or equal to twice the transconductance of a second transistor. The compensation signal is supplied through a capacitor, which compensates for capacitors in a VCO, to an internal supply node of the VCO. At the internal supply node, the compensation signal removes (or greatly reduces) the noise introduced by the supply signal noise, resulting in a less-noisy output signal from the VCO. | 12-18-2014 |
Patent application number | Description | Published |
20080222244 | METHOD AND APPARATUS FOR ACCELERATION BY PREFETCHING ASSOCIATED OBJECTS - Association information is used to build association trees to associate base pages and embedded objects at a proxy. An association tree has a root node containing a URL for a base page, and zero or more leaf nodes each containing a URL for an embedded object. In most cases, an association tree will maintain the invariant that all leaves contain distinct URLs. However, it is also possible to have an association tree in which the same URL appears in multiple nodes. An association tree may optionally contain one or more internal nodes, each of which contains a URL that is an embedded object for some other base page, but which may also be fetched as a base page itself. Given a number of association trees and a base-page URL, a prefetch system finds the root or interior node corresponding to that URL (if any) and traverses the tree from that node, prefetching URLs until the URL of the last leaf node is prefetched. The prefetching starts the process of bringing over the various embedded objects before the user or program would ordinarily fetch them. | 09-11-2008 |
20090119504 | INTERCEPTING AND SPLIT-TERMINATING AUTHENTICATED COMMUNICATION CONNECTIONS - Systems and methods are provided for enabling optimization of communications within a networked computing environment requiring secure, authenticated client-server communication connections. Optimization is performed by a pair of intermediary network devices installed in a path of communications between the client and the server. A secure, authenticated communication connection between the client and server is split-terminated at a pair of intermediary network devices by intercepting a request from the client for a client-server connection, authenticating the client at the intermediaries, establishing a first secure, authenticated connection to the client, authenticating the client or an intermediary to the server, and establishing a second secure, authenticate connection to the server. Depending on the operative authentication protocol (e.g., NTLM, Kerberos), an intermediary may interface with a domain controller, key distribution center or other entity. | 05-07-2009 |
20100049970 | METHODS AND SYSTEMS FOR SECURE COMMUNICATIONS USING A LOCAL CERTIFICATION AUTHORITY - A local network traffic processor and an application are resident on a common computer system. The application is configured to trust a server certificate issued by a local network traffic processor, the local network traffic processor operatively being paired with a remote network traffic processor. A proxy server certificate, generated using identification information of a server associated with the remote network traffic processor and signed by the local certification authority, is used to establish a secure session between a local network traffic processor and the application. | 02-25-2010 |
20100228968 | SPLIT TERMINATION OF SECURE COMMUNICATION SESSIONS WITH MUTUAL CERTIFICATE-BASED AUTHENTICATION - A method and apparatus are provided for split-terminating a secure client-server communication connection when the client and server perform mutual authentication by exchanging certificates, such as within a Lotus Notes environment. When the client submits a certificate to the server, an intermediary device intercepts the certificate and submits to the server a substitute client certificate generated by that intermediary. A certificate authority's private key is previously installed on the intermediary to enable it to generate public keys, private keys and digital certificates. With the private key corresponding to the substitute certificate, the intermediary extracts a temporary key from a subsequent server message. The intermediary uses the temporary key to read a session key issued later by the server. Thereafter, the intermediary shares the session key with another intermediary, and together they use the session keys to access and optimize (e.g., accelerate) messages sent by the client and the server. | 09-09-2010 |
20100241673 | VIRTUALIZED DATA STORAGE SYSTEM ARCHITECTURE - Virtual storage arrays consolidate branch data storage at data centers connected via wide area networks. Virtual storage arrays appear to storage clients as local data storage; however, virtual storage arrays actually store data at the data center. The virtual storage arrays overcomes bandwidth and latency limitations of the wide area network by predicting and prefetching storage blocks, which are then cached at the branch location. Virtual storage arrays leverage an understanding of the semantics and structure of high-level data structures associated with storage blocks to predict which storage blocks are likely to be requested by a storage client in the near future. Virtual storage arrays determine the association between requested storage blocks and corresponding high-level data structure entities to predict additional high-level data structure entities that are likely to be accessed. From this, the virtual storage array identifies the additional storage blocks for prefetching. | 09-23-2010 |
20100241807 | VIRTUALIZED DATA STORAGE SYSTEM CACHE MANAGEMENT - Virtual storage arrays consolidate branch data storage at data centers connected via wide area networks. Virtual storage arrays appear to storage clients as local data storage; however, virtual storage arrays actually store data at the data center. The virtual storage arrays overcomes bandwidth and latency limitations of the wide area network by predicting and prefetching storage blocks, which are then cached at the branch location. Virtual storage arrays leverage an understanding of the semantics and structure of high-level data structures associated with storage blocks to predict which storage blocks are likely to be requested by a storage client in the near future. Virtual storage arrays determine the association between requested storage blocks and corresponding high-level data structure entities to predict additional high-level data structure entities that are likely to be accessed. From this, the virtual storage array identifies the additional storage blocks for prefetching. | 09-23-2010 |
20100318665 | INTERCEPTION OF A CLOUD-BASED COMMUNICATION CONNECTION - Methods and apparatus are provided for intercepting a client-server communication connection in a computing environment. A first network intermediary configured to facilitate optimization of client-server transactions may be installed in a path of communications between the client and the server. A second network intermediary configured to cooperate with the first network intermediary is not in the path of communications between the client and the server. The first network intermediary intercepts a connection request from the client and forwards a modified request toward the server. A module within the server intercepts the connection request and redirects it to the second network intermediary. The client-server connection is thus split-terminated at the two network intermediaries, which establish cooperative sessions between themselves and with the client and with the server. | 12-16-2010 |
20120030456 | Booting Devices Using Virtual Storage Arrays Over Wide-Area Networks - Virtual storage arrays consolidate data storage at a data center for physical and virtual computer systems at one or more branch network locations. Standalone and virtualized computer systems at a branch network location load, execute, and store their operating systems, applications, and data using virtual storage arrays and do not require any built-in or external non-volatile data storage devices such as hard disk drives or solid-state drives at the branch network location. The virtual disks of the virtual storage array are mapped to physical data storage at the data center and accessed via a WAN using storage block-based protocols. A storage block cache at the branch network location includes storage blocks prefetched based on knowledge about the computer systems at the branch network location and the behavior of their operating systems and applications. | 02-02-2012 |
20130232215 | VIRTUALIZED DATA STORAGE SYSTEM ARCHITECTURE USING PREFETCHING AGENT - Virtual storage arrays consolidate data storage from branch locations at data centers. The virtual storage array appears to storage clients as a local data storage; however, the virtual storage array data is actually stored at a data center. To overcome the bandwidth and latency limitations of wide area networks between branch locations and the data center, systems and methods predict, prefetch, and cache at the branch location storage blocks that are likely to be requested in the future by storage clients. When this prediction is successful, storage block requests are fulfilled from branch locations' storage block caches. Predictions may leverage an understanding of the semantics and structure of the high-level data structures associated with the storage blocks. Prefetching agents on storage clients monitor storage requests to determine the associations between requested storage blocks and the corresponding high-level data structures as well as other attributes useful for prediction. | 09-05-2013 |
20130297854 | ENSURING WRITE OPERATION CONSISTENCY USING RAID STORAGE DEVICES - Solid-state storage devices (SSD) are combined with larger capacity magnetic disk-based RAID arrays for storing write data to ensure data consistency across multiple RAID disks. Write operations are stored in a sequential write buffer in at least one SSD to guarantee their storage and then copied from the sequential write buffer to the destination address in RAID array. The sequential write buffer stores write data in locations corresponding to the order of receipt of write operations. Write data from the sequential write buffer is transferred to the RAID array in the same order and a checkpoint index is frequently updated to indicate the completion of some transfers. During system initialization, a copy of the sequential write buffer and its associated checkpoint index are retrieved and used as a starting location for transferring write data from the sequential write buffer to the magnetic disk storage devices in the RAID array. | 11-07-2013 |
20130297855 | ENSURING WRITE OPERATION CONSISTENCY USING MULTIPLE STORAGE DEVICES - Relatively small capacity solid-state storage devices (SSD) are combined with larger capacity magnetic disk storage devices for storing storage block write data to ensure data consistency. Write operations are stored in a sequential write buffer in an SSD to guarantee the storage of write data and then copied from the sequential write buffer to the destination address in a magnetic disk storage device. The sequential write buffer store write data in locations corresponding to the order of receipt of write operations. Write data from the sequential write buffer is transferred to the magnetic disk storage device in the same order and a checkpoint index is frequently updated to indicate the completion of some transfers. During system initialization, the most recent value of the checkpoint index is retrieved and used as a starting location for transferring write data from the sequential write buffer to the magnetic disk storage device. | 11-07-2013 |
Patent application number | Description | Published |
20100106798 | MULTIMEDIA REDIRECTION - A system for receiving redirected electronic media playback includes a proxy configured to communicate with a remote access module. The remote access module is configured to establish a remote access connection between the system and a remote system. The proxy is configured to receive, over the remote access connection, a decode request for electronic media content designated for a local multimedia application on the system, and in return, provide a result for the request. The proxy is also configured to receive at least one playback command designated for playing the electronic media content on the local multimedia application. The electronic media appears to be playing on a remote multimedia application on the remote system corresponding to the local multimedia application, but is played on the local multimedia application. A system for redirecting playback of electronic media content to a remote system, methods, and machine-readable media are also provided. | 04-29-2010 |
20110194564 | Distributing Ethernet Alarm Indication Signal Information to Multiple Virtual Local Area Networks - Ethernet Alarm Indication Signal (ETH-AIS) information for multiple Virtual Local Area Networks (VLANs) is consolidated and distributed to the multiple VLANs in a single Ethernet frame. Note, as used herein, “Alarm Indication Signal (ETH-AIS)” refers to an IEEE 802.x or ITU-T Y.1731 Ethernet Alarm Indication Signal. A device receiving the Ethernet frame with the consolidated ETH-AIS information typically forwards the frame out each port that communicates traffic for one of the VLANs included in the consolidated ETH-AIS information. | 08-11-2011 |
20110246696 | Interrupt Vector Piggybacking - A hypervisor receives an interrupt that includes a target address and, in turn, branches to an administrating interrupt vector. Next, the administrating interrupt vector determines whether to branch to a piggyback interrupt handler corresponding to a piggyback interrupt vector. Based upon the determination, the hypervisor either branches to the piggyback interrupt handler or to an administrating interrupt handler that corresponds to the administrating interrupt vector. | 10-06-2011 |
20150082401 | METHOD AND DEVICE FOR FACILITATING MUTUAL AUTHENTICATION BETWEEN A SERVER AND A USER USING HAPTIC FEEDBACK - A method is provided for facilitating mutual authenticating between a server and a user of a haptic enabled device. The method comprises providing identity information of a user to a server, and in response, providing a haptic feedback output to the user corresponding to the identity information. Further, the user compares the haptic feedback output received from the server to a haptic feedback pattern as predefined by the user, to determine whether the server is authenticated or not. | 03-19-2015 |
Patent application number | Description | Published |
20120059708 | Mapping Advertiser Intents to Keywords - In one embodiment, a method includes constructing an intent map for a plurality of products, the intent map comprising intent topics and each intent topic comprising intents, and then deriving a plurality of keywords from the intent map based on keyword templates. | 03-08-2012 |
20120059713 | Matching Advertisers and Users Based on Their Respective Intents - In one embodiment, a method includes deriving a user intent from user information associated with a user, selecting an advertiser intent that aligns with the user intent, and then advertising to the user based on the advertiser intent that aligns with the user intent. | 03-08-2012 |
20130114439 | AUTOMATIC FRAMING SELECTION - Network traffic is monitored and an optimal framing heuristic is automatically determined and applied. Framing heuristics specify different rules for framing network traffic. While a framing heuristic is applied to the network traffic, alternative framing heuristics are speculatively evaluated for the network traffic. The results of these evaluations are used to rank the framing heuristics. The framing heuristic with the best rank is selected for framing subsequent network traffic. Each client/server traffic flow may have a separate framing heuristic. The framing heuristics may be deterministic based on byte count and/or time or based on traffic characteristics that indicate a plausible point for framing to occur. The choice of available framing heuristics may be determined partly by manual configuration, which specifies which framing heuristics are available, and partly by automatic processes, which determine the best framing heuristic to apply to the current network traffic from the set of available framing heuristics. | 05-09-2013 |
20140071824 | SERIAL CLUSTERING - Serial clustering uses two or more network devices connected in series via a local and/or wide-area network to provide additional capacity when network traffic exceeds the processing capabilities of a single network device. When a first network device reaches its capacity limit, any excess network traffic beyond that limit is passed through the first network device unchanged. A network device connected in series with the first network device intercepts and will process the excess network traffic provided that it has sufficient processing capacity. Additional network devices can process remaining network traffic in a similar manner until all of the excess network traffic has been processed or until there are no more additional network devices. Network devices may use rules to determine how to handle network traffic. Rules may be based on the attributes of received network packets, attributes of the network device, or attributes of the network. | 03-13-2014 |
Patent application number | Description | Published |
20120161823 | FREQUENCY DIVISION OF AN INPUT CLOCK SIGNAL - Circuitry and method for dividing the frequency of an input clock signal for use in a prescaler of a digital frequency synthesizer. A flip flop is clocked on a first type of edge of the input clock signal, and provides an output for use as a divided clock signal. Feedback circuitry is clocked on the first type of edge of the input clock signal and provides a signal to a data input of the flip flop based on the inverse of the output of the flip flop. In a first mode the feedback circuitry is arranged to allow the signal provided to the data input of the flip flop to follow the inverse of the output of the flip flop so that each first type of edge causes the signal provided to the data input of the flip flop to toggle such that the output of the flip flop has a frequency which is substantially half of the frequency of the input clock signal, and wherein in a second mode the feedback circuitry is arranged to allow the signal provided to the data input of the flip flop to follow the inverse of the output of the flip flop with the exception that toggling of the signal provided to the data input of the flip flop is selectively prevented despite toggling of the output of the flip flop on an edge of the first type such that the output of the flip flop has a frequency which is at most a third of the frequency of the input clock signal. The feedback circuitry is arranged to operate independently from a second type of edge of the input clock signal in providing the signal to the data input of the flip flop, such that the output of the flip flop is independent from the duty cycle of the input clock signal. | 06-28-2012 |
20120169393 | PROCESSING CLOCK SIGNALS - A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit including an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; a first pass gate for receiving the inverted clock edge and outputting a first trigger signal of a first polarity; and a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal. | 07-05-2012 |
20140247035 | NOISE CANCELING CURRENT MIRROR CIRCUIT FOR IMPROVED PSR - A current mirror circuit provides a current to drive a load. A noise cancelling circuit is provided to keep the load current constant in spite of variations in the supply voltage. The noise cancelling circuit includes an auxiliary current path which branches from the load current path. The length-to-width ratios of transistors of the circuit are selected to provide the desired noise cancellation while maintaining device stability. | 09-04-2014 |
20140300386 | VOLTAGE LEVEL SHIFTER CIRCUIT, SYSTEM, AND METHOD FOR HIGH SPEED APPLICATIONS - A level shifting circuit includes a first inverter including a pair of transistors of opposite conductivity type, the first inverter adapted to receive an input signal in a first voltage domain and further including at least one additional transistor driven by a voltage in a second voltage domain. A second inverter is coupled in series with the first inverter and operable to generate an output signal in the second voltage domain. The second inverter includes a pair of transistors of opposite conductivity type, and further includes at least one additional transistor driven by a voltage in the first voltage domain. The additional transistors are operable to approximately equalize the fall times of output signals generated by the first and second inverters. | 10-09-2014 |
Patent application number | Description | Published |
20130184455 | CONJUGATES COMPRISING HYDROXYALKYL STARCH AND A CYTOTOXIC AGENT AND PROCESS FOR THEIR PREPARATION - The present invention relates to a hydroxyalkyl starch conjugate and a method for preparing the same, said hydroxyalkyl starch conjugate comprising a hydroxyalkyl starch derivative and a cytotoxic agent, the cytotoxic agent comprising at least one secondary hydroxyl group, wherein the hydroxyalkyl starch is linked via said secondary hydroxyl group to the cytotoxic agent. The conjugate according to the present invention has a structure according to the following formula HAS′(-L-M) | 07-18-2013 |
20130211060 | CONJUGATES COMPRISING HYDROXYALKYL STARCH AND A CYTOTOXIC AGENT AND PROCESS FOR THEIR PREPARATION - The present invention relates to a hydroxyalkyl starch conjugate and a method for preparing the same, said hydroxy-yalkyl starch conjugate comprising a hydroxyalkyl starch derivative and a cytotoxic agent, the cytotoxic agent comprising at least one secondary hydroxyl group, wherein the hydroxyalkyl starch is linked via said secondary hydroxyl group to the cytotoxic agent. The conjugate according to the present invention has a structure according to the following formula HAS′(-L-M) | 08-15-2013 |
20130217871 | CONJUGATES COMPRISING HYDROXYALKYL STARCH AND A CYTOTOXIC AGENT AND PROCESS FOR THEIR PREPARATION - The present invention relates to hydroxyalkyl starch conjugates and a method for preparing the same, the hydroxyalkyl starch conjugate comprising a hydroxyalkyl starch derivative and a cytotoxic agent, the cytotoxic agent comprising at least one primary hydroxyl group, wherein the hydroxyalkyl starch is linked via said primary hydroxyl group to the cytotoxic agent. The conjugates according to the present invention have a structure according to the following formula HAS′(-L-M) | 08-22-2013 |
20140058119 | PROCESS FOR THE PREPARATION CABAZITAXEL - The present invention discloses a process for the preparation of 4-acetoxy-2α-benzoyloxy-5β,20-epoxy-1-hydroxy-7β,10β-dimethoxy-9-oxotax-11-en-13α-yl(2R,3S)-3-tert-butoxycarbonylamino-2-hydroxy-3-phenyl-propionate Cabazitaxel (I). | 02-27-2014 |
20140073779 | CONJUGATES COMPRISING HYDROXYALKYL STARCH AND A CYTOTOXIC AGENT AND PROCESS FOR THEIR PREPARATION - The present invention relates to a hydroxyalkyl starch conjugate and a method for preparing the same, said hydroxyalkyl starch conjugate comprising a hydroxyalkyl starch derivative and a cytotoxic agent, the cytotoxic agent comprising at least one secondary hydroxyl group, wherein the hydroxyalkyl starch is linked via said secondary hydroxyl group to the cytotoxic agent. The conjugate according to the present invention has a structure according to the following formula HAS′(-L-M) | 03-13-2014 |
20140088298 | CONJUGATES COMPRISING HYDROXYALKYL STARCH AND A CYTOTOXIC AGENT AND PROCESS FOR THEIR PREPARATION - The present invention relates to a hydroxyalkyl starch conjugate and a method for preparing the same, said hydroxy-yalkyl starch conjugate comprising a hydroxyalkyl starch derivative and a cytotoxic agent, the cytotoxic agent comprising at least one secondary hydroxyl group, wherein the hydroxyalkyl starch is linked via said secondary hydroxyl group to the cytotoxic agent. The conjugate according to the present invention has a structure according to the following formula HAS′(-L-M) | 03-27-2014 |
20150057454 | PROCESS FOR THE PREPARATION OF CABAZITAXEL - The present invention discloses a process for the preparation of 4-acetoxy-2α-benzoyloxy-5β,20-epoxy-1-hydroxy-7β,10β-dimethoxy-9-oxotax-11-en-13α-yl(2 R,35)-3-tert-butoxycarbonylamino-2-hydroxy-3-phenyl-propionate Cabazitaxel (I). | 02-26-2015 |