Patent application number | Description | Published |
20090004981 | HIGH EFFICIENCY DIGITAL TRANSMITTER INCORPORATING SWITCHING POWER SUPPLY AND LINEAR POWER AMPLIFIER - A novel apparatus and method of improving the power efficiency of a digital transmitter for non-constant-amplitude modulation schemes. The power efficiency improvement mechanism of the invention leverages the high efficiency of a switched-mode power supply (SMPS) that supplies the high DC current to the transmitter's power amplifier, while compensating for its limitations using predistortion. The predistortion may be achieved using any suitable technique such as digital signal processing, hardware techniques, etc. A switched mode power supply (i.e. switching regulator) is used to provide a slow form (i.e. reduced bandwidth) of envelope tracking (based on a narrower bandwidth distorted version of the envelope waveform) such that the switching regulator can use a lower switching rate corresponding to the lower bandwidth, thereby obtaining high efficiency in the switching regulator. The resulting AM-AM and AM-PM distortions in the power amplifier are compensated through predistortion of the digital amplitude modulating signal which dictates the envelope at the PA input. Similarly, the phase modulation is also compensated prior to the PA, such that once it undergoes the distortion in the PA, the end result is sufficiently close to the desired phase. | 01-01-2009 |
20090257396 | System and method of adaptive frequency hopping with look ahead interference prediction - A novel and useful adaptive frequency hopping scheme for wireless devices and networks operating in a congested environment of similar devices, where capacity maximization is desired. The hopping sequence of each wireless link is dynamically adapted such that the impact of the surrounding interference is minimized and the interference induced onto the coexisting systems is also minimized. The scheme detects the repetitive presence of interference on a particular channel and comprises a replacement mechanism for swapping the interfered frequency-channel with one that would be clear for that particular time-slot. The mechanism detects interference during a redundant portion of the transmission (i.e. header or trailer) without having to experience packet failures (i.e. data loss). If the interference impact (e.g. corrupted header bits) exceeds a predefined threshold, that frequency channel is declared temporarily unusable for that time slot and is replaced with another in accordance with a frequency replacement policy. Periodic interference at a particular frequency, originating from a coexisting system of similar operating parameters, may also be detected at instances that are distant from the timeslots for which that particular frequency is to be used, such that frequency replacement in the hopping sequence can be scheduled ahead of time and collisions would be avoided altogether. | 10-15-2009 |
20100008338 | HIGH TRANSMISSION POWER USING SHARED BLUETOOTH AND WIRELESS LOCAL AREA NETWORK FRONT END MODULE - A novel and useful system for providing high transmission power using a shared Bluetooth and Wireless Local Area Network (WLAN) front end module (FEM). A single power amplifier in the front end module is shared between the WLAN and Bluetooth radio cores, thus providing a high power transmission option (Bluetooth class 1) for the Bluetooth core. Interface circuitry in the FEM couple either the WLAN TX output or the Bluetooth TX output to the input of the power amplifier and couple the output of the power amplifier to the external antenna. In the receive direction, the interface circuitry steers the antenna input to the respective WLAN or Bluetooth receivers in accordance with one or more control signals. Alternatively, a switch in the WLAN/Bluetooth radio chip functions to switch the Bluetooth TX output to a conventional FEM, thereby allowing the FEM power amplifier to be shared between the WLAN and Bluetooth radio cores. | 01-14-2010 |
20120082008 | Low Power Radio Controlled Clock Incorporating Independent Timing Corrections - A timekeeping device that tracks the time provided by a digital broadcast and the protocol of that broadcast, defined by its data frame structure and modulation scheme, are adapted to allow for superior performance of the timekeeping devices in terms of range of operation, immunity to interference, ability to operate with lower cost antennas due to enhanced link robustness, and reduced energy consumption. The timekeeping device operates with infrequent receptions of the broadcast by relying on independent self-compensation. This alleviates the need for frequent receptions to ensure timing accuracy while reducing energy consumption. The mean and variability of successive measurements of timing drift are evaluated and an estimated upper bound for the drift-estimation error is set. Based on this bound, the device employs a reception strategy that relies on less frequent receptions, corresponding to the error in estimating the drift rather than to the magnitude of the drift itself | 04-05-2012 |
20120093204 | PROCESSOR, MODEM AND METHOD FOR CANCELLING ALIEN NOISE IN COORDINATED DIGITAL SUBSCRIBER LINES - A method of cancelling alien noise in coordinated DSL lines, a method of smoothing an alien noise covariance estimate, and a processor and modem for cancelling alien noise in coordinated DSL lines. In one embodiment, the method of cancelling alien noise includes: (1) estimating alien noise vectors for at least some training symbols, (2) arranging the alien noise vectors in a matrix dimensioned for a number of coordinated DSL lines, (3) orthonormally transforming the matrix into a lower-triangular matrix and (4) computing alien noise prediction filters from the lower-triangular matrix. | 04-19-2012 |
20120169397 | Mixed Signal Integrator Incorporating Extended Integration Duration - A mixed-signal integrator, having an analog input and a digital output, is adapted to perform an integration operation partially in the analog domain and partially in the digital domain while eliminating the limitations of a conventional analog integrator. The integrator also digitizes a signal of interest without the use of a conventional sampling operation followed by a conventional analog-to-digital converter. The analog integrator portion generates an analog integration signal limited between low and high rail voltages defined by two comparators with corresponding threshold voltages. When either rail voltage is reached, the polarity of the input signal is reversed to prevent the integration result from exceeding that rail. Each such event is also tracked in digital logic, which provides a count whenever two consecutive such events correspond to the two different rails. At the end of the integration duration this count serves as the digital representation of the integration result. | 07-05-2012 |
20120244824 | MINIMIZATION OF RMS PHASE ERROR IN A PHASE LOCKED LOOP BY DITHERING OF A FREQUENCY REFERENCE - A novel and useful apparatus for and method of minimizing the phase distortions experienced at the output of a phase locked loop (PLL) by dithering of its input frequency reference to overcome additive interference that is parasitically suffered on it. The frequency reference signal is dithered in a controlled manner using either indirect or direct coupling. The dither signal may be a single clock or is generated by switching between two or more of the existing clock signals generated, or may be produced by a dedicated pseudo-random noise generator having specific spectral properties. In indirect coupling, the dither signal is coupled through a bond wire sufficiently close in proximity to the frequency reference circuit input. This dominates the jitter inflicted onto the frequency reference signal and upconverts its spectral content to higher frequency, thus eliminating the more damaging low-frequency jitter caused by the interfering RF signal. In direct coupling, the dither signal is coupled to the reference frequency input using a network of components directly connected thereto. | 09-27-2012 |
20120252382 | PREDISTORTION CALIBRATION AND BUILT IN SELF TESTING OF A RADIO FREQUENCY POWER AMPLIFIER USING SUBHARMONIC MIXING - A novel and useful apparatus for and method of predistortion calibration and built-in self testing (BIST) of a nonlinear digitally-controlled radio frequency (RF) power amplifier (DPA) using subharmonic mixing. The RF power amplifier output is temporarily coupled into the frequency reference (FREF) input and the phase error samples generated in the phase locked loop (PLL) are then observed and analyzed. The digital predistortion and BIST mechanisms process the phase error samples to calibrate and test the DPA in the transmitter of the Digital RF Processor (DRP). The invention enables the characterization of nonlinearities, the configuration of internal predistortion, as well as the testing of the transmitter's analog/RF circuitry, thereby eliminating commonly employed RF performance testing using high-cost test equipment and associated extended test times. | 10-04-2012 |
20120263256 | LINEARIZATION OF A TRANSMIT AMPLIFIER - An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion calibration to compensate for nonlinearlities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital-to-frequency converter (DFC), DPA and PA. The on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, demodulates the RF PA output and uses the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. A sample of the RF output signal is provided to the receiver chain. While the PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed. | 10-18-2012 |
20130114451 | INTRA-CELL AND INTER-CELL INTERFERENCE MITIGATION METHODS FOR ORTHOGONAL FREQUENCY-DIVISION MULTIPLE ACCESS CELLULAR NETWORKS - Various embodiments of a method of mitigating interference in an OFDMA cellular network and a user terminal incorporating various of the embodiments. In one embodiment, the method includes: (1) selecting at least one dominant interfering signal, (2) generating estimates of a desired signal and the at least one dominant interfering signal, (3) jointly deciding based on the estimates such that an energy of a residual error is reduced and (4) mitigating interference based on the estimates. | 05-09-2013 |
20130121117 | LEAP SECOND AND DAYLIGHT SAVING TIME CORRECTION FOR USE IN A RADIO CONTROLLED CLOCK RECEIVER - A novel and useful system and method for leap second and daylight saving time (DST) correction for use in a radio controlled clock (RCC) receiver. The RCC receiver extracts schedule information from the frame, including the time for the DST transition and whether a leap second needs to be added at the end of this half-year. Linear error correcting coding is used for the leap second and the DST on/off indications, while non-linear error correcting coding (e.g., a look up table) is used for the DST schedule to enhance reception reliability in the presence of noise and interference. The one second/one hour corrections are scheduled to occur when they should take place and the correction is applied exactly when DST or leap second is to go into effect, without having to receive anything around the time of the correction. | 05-16-2013 |
20130121118 | Leap Second and Daylight Saving Time Correction in a Radio Controlled Clock Receiver - A novel and useful system and method for leap second and daylight saving time (DST) correction for use in a radio controlled clock (RCC) receiver. The RCC receiver extracts schedule information from the frame, including the time for the DST transition and whether a leap second needs to be added at the end of this half-year. Linear error correcting coding is used for the leap second and the DST on/off indications, while non-linear error correcting coding (e.g., a look up table) is used for the DST schedule to enhance reception reliability in the presence of noise and interference. The one second/one hour corrections are scheduled to occur when they should take place and the correction is applied exactly when DST or leap second is to go into effect, without having to receive anything around the time of the correction. | 05-16-2013 |
20130121397 | System and Method for Phase Modulation Over a Pulse Width Modulated/Amplitude Modulated Signal for Use in a Radio Controlled Clock Receiver - A system and method for a radio controlled clock receiver adapted to extract timing and time information from a phase modulated signal. The official time signal is broadcast from a central location using a modified modulation scheme, which adds phase modulation over the legacy amplitude modulation, such as the legacy WWVB pulse width modulated (PWM)/amplitude shift keying (ASK) modulation, thereby allowing for improved performance. The information modulated onto the phase contains a known synchronization sequence having good autocorrelation properties, error-correcting coding for the time information and notifications of daylight-saving-time (DST) transitions that are provided months in advance. The modulation scheme is based on a form of phase modulation, such as binary-phase-shift-keying (BPSK) or phase reversal keying (PRK). The reception of multiple frames with repeated or sequential information allows for the accumulation of received energy over multiple frames to provide for a corresponding gain in the receiver. | 05-16-2013 |
20130121398 | Timing and Time Information Extraction from a Phase Modulated Signal in a Radio Controlled Clock Receiver - A system and method for a radio controlled clock receiver adapted to extract timing and time information from a phase modulated signal. The official time signal is broadcast from a central location using the modified modulation scheme of the present invention, which adds phase modulation that allows for greatly improved performance. The information modulated onto the phase contains a known synchronization sequence having good autocorrelation properties, error-correcting coding for the time information and notifications of daylight-saving-time (DST) transitions that are provided months in advance. The modulation scheme is based on a form of phase modulation, such as binary-phase-shift-keying (BPSK) or phase reversal keying (PRK). A superframe comprising multiple frames with repeated information allows for the accumulation of received energy over multiple frames to provide for a corresponding gain in the receiver. | 05-16-2013 |
20130121399 | Timing and Time Information Extraction in a Radio Controlled Clock Receiver - A novel and useful system and method for extracting timing, time and additional information from a broadcast received in a radio controlled clock (RCC) receiver. The RCC receiver extracts timing information represented by a known synchronization sequence that is used for acquisition and tracking purposes. The RCC receiver extracts time information as a merged 26-bit time information word linearly coded into 31 bits comprising the number of minutes (or hours) since the turn of the current century. A minute counter representing the 26 bits is converted into the date, hour, and minute. The RCC extracts additional information including the schedule for the next daylight saving time transition and for an imminent leap second. The communications protocol optionally employs error correcting codes to provide protection for data fields in the frame, which the RCC may use to enhance reception reliability in the presence of noise and interference. | 05-16-2013 |
20130121400 | ADAPTIVE RADIO CONTROLLED CLOCK EMPLOYING DIFFERENT MODES OF OPERATION FOR DIFFERENT APPLICATIONS AND SCENARIOS - A configurable system and method for a radio controlled clock (RCC) receiver adapted to apply different strategies for extracting timing and time information from a phase modulated signal depending on the type of application the RCC is used in and on the reception conditions. The official time signal is broadcast from a central location using a modulation scheme which includes phase modulation that alternates between different information rates, allowing for multiple alternative reception modes that are suited for different ranges of signal-to-interference-and-noise-ratio (SINR). The operation of the RCC is configured by the application that hosts it, such that the reception performance and the energy consumption best suit that application. The reception mode used by the RCC at a given time may be selected automatically, i.e. without user intervention, based on the device's profile of operation and the reception conditions. | 05-16-2013 |
20130230094 | MULTI-ANTENNA RECEIVER IN A RADIO CONTROLLED CLOCK - A novel and useful multi-antenna receiver that receives, demodulates and decodes a broadcast signal, whose modulation and encoding of time and timing information allow for reliable and power-efficient operation. The multi-antenna receiver of the present invention is adapted to eliminate or substantially reduce the reception nulls that occur in receivers having a single antenna that is placed in a fixed position. Two or more antennas are employed whereby the receiver generates a combined signal based on a combination of the individual antenna signals or selects one of the antenna signals for input to the receiver based on desired criteria such as signal-to-noise-and-interference-ratio (SNIR). This results in greater robustness of the communication link by reducing or eliminating reception nulls and by rejecting interference through the selection of the antenna for which the signal-to-interference ratio is higher. The invention includes various antenna configurations that are adapted to reuse a single core for multiple antennas or to otherwise reduce size and/or cost. | 09-05-2013 |
20130234871 | SELF-COMPENSATING DIGITAL-TO-ANALOG CONVERTER AND METHODS OF CALIBRATION AND OPERATION THEREOF - Cost-effective structures and methods that allow an integrated digital-to-analog converter (DAC) to simultaneously achieve wide dynamic ranges and bandwidths through the use of built-in measurement and compensation mechanisms that are primarily digital. The measurements of the DAC's distortions are made with a relatively simple analog-to-digital converter (ADC) that is not designed to accommodate the combination of the bandwidth and the resolution offered by the DAC, but is nonetheless sufficient in determining the characteristics of the DAC's impairments during a calibration procedure. This information is then used in a feed-forward compensation system during the DAC's normal operation to estimate and cancel the distortions in its output signal that could result from the various impairments. | 09-12-2013 |
20140050315 | HIGH-SPEED IN-MEMORY QR DECOMPOSITION USING FAST PLANE ROTATIONS - A system and method for processing an input matrix and a MIMO receiver employing the system or the method. In one embodiment, the system includes: (1) a transformer configured to receive a frame of complex data representing only some elements of an input matrix and perform a fast plane rotation on the complex data to yield rotated data and (2) a matrix updater coupled to the transformer and configured to update a memory configured to contain an output matrix with the rotated data. In one embodiment, the system and method are to estimate and mitigate alien cross-talk experienced in a vectored DSL communication system. | 02-20-2014 |