Patent application number | Description | Published |
20150049406 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT ARRANGEMENT, ELECTRONIC CIRCUIT AND ESD PROTECTION METHOD - An electrostatic discharge, ESD, protection circuit arrangement is connectable to a first pin and a second pin of an electronic circuit and arranged to at least partly absorb an ESD current entering the electronic circuit through at least one of the first pin or the second pin during an ESD stress event. The protection circuit arrangement comprises a first ESD protection circuit arranged to absorb a first portion of the ESD current during a first part of the ESD stress event during which first part a level of the ESD current exceeds a predetermined current threshold; and a second ESD protection circuit arranged to absorb a second portion of the ESD current, the second portion having a current level below the current threshold, at least during a second part of the ESD stress event. The second ESD protection circuit comprises a current limiting circuit arranged to limit a current through at least a portion of the second ESD protection circuit to the current threshold. | 02-19-2015 |
20150061728 | ELECTRONIC DEVICE AND METHOD FOR MAINTAINING FUNCTIONALITY OF AN INTEGRATED CIRCUIT DURING ELECTRICAL AGGRESSIONS - An electronic device for generating an error signal in response to an electrostatic discharge perturbation is described. The device may comprise: a detection unit for generating a detection signal in response to said electrostatic discharge perturbation, said detection signal correlating in time with said electrostatic discharge perturbation; a clock for generating a clock signal having a clock period; and a protection unit for generating an error signal in response to said detection signal only when a duration of said detection signal exceeds a predefined multiple of said clock period. A method of generating an error signal in response to an electrostatic discharge perturbation, for protecting electronic circuitry, is also disclosed. | 03-05-2015 |
20150076556 | INTEGRATED CIRCUIT DEVICE AND A METHOD FOR PROVIDING ESD PROTECTION - An integrated circuit (IC) device including an electrostatic discharge (ESD) protection network for a high voltage application. The ESD protection network includes a common diode structure coupled between an external contact of the IC device and a substrate of the IC device, such that the common diode structure is forward biased towards the external contact, a Darlington transistor structure coupled between the external contact and the substrate of the IC device, and the Darlington transistor structure includes: an emitter node coupled to the external contact; a collector node coupled to the substrate; and a base node coupled between the emitter node of the Darlington transistor structure and the common diode structure. The at least one ESD protection network further comprises an isolation diode structure coupled between the emitter node and the base node of the Darlington transistor structure such that the isolation diode structure is forward biased towards the base node. | 03-19-2015 |
20150098160 | PROTECTION CIRCUIT AND A GATE DRIVING CIRCUITRY - A protection circuit and a gate driving circuitry. The protection circuit is for protecting a p-type back-to-back MOS switch. The circuit receives an input driving signal and provides a driving output signal to common gates of the p-type back-to-back MOS switch. The circuit comprises a driving signal insulation switch for disconnecting the common gate of the p-type back-to-back MOS switch from the received input driving signal when the voltage of the common gates is larger than the supply voltage of the circuit. The circuit further comprises a gate source coupling switch for coupling a voltage received at the common source of the p-type back-to-back MOS switch to the common gate if a received voltage at the common sources is larger than a reference voltage Vref. | 04-09-2015 |
20150129928 | PACKAGED SEMICONDUCTOR DEVICE, A SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A PACKAGED SEMICONDUCTOR DEVICE - A packaged semiconductor device comprising a package and a semiconductor device is described. The semiconductor device comprises a first and a second GND-pad bonded to one or more GND-pins with a first and a second bond wire respectively, a first functional pad bonded to a first functional pin with a third bond wire, a semiconductor layer of a P-type conductivity, a first semiconductor component and a second semiconductor component. The first semiconductor component is arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current to the first GND-pad from the first P-region to the first GND-pad via at least a first PN-junction. The second semiconductor component comprises a second N-type region of a terminal of the second semiconductor component associated with the first functional pad. The first GND-pad is in contact with a second P-type region. The second GND-pad is in contact with a third N-type region. At least part of the second P-type region is arranged in between the first semiconductor component and the second semiconductor component, and at least part of the third N-type region is arranged in between the at least part of the first P-type region and the second semiconductor component. | 05-14-2015 |
20150221629 | SEMICONDUCTOR DEVICE AND AN INTEGRATED CIRCUIT COMPRISING AN ESD PROTECTION DEVICE, ESD PROTECTION DEVICES AND A METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in which a structure is manufactured which operates as a Silicon Controlled Rectifier which is coupled between an I/O pad and a reference voltage or ground voltage. The semiconductor device also comprises a pnp transistor which is coupled parallel to the Silicon Controlled Rectifier. The base of the transistor is coupled to the gate of the Silicon Controlled Rectifier. In an optional embodiment, the base and gate are also coupled to the I/O pad. | 08-06-2015 |
20150221633 | SEMICONDUCTOR DEVICE COMPRISING AN ESD PROTECTION DEVICE, AN ESD PROTECTION CIRCUITRY, AN INTEGRATED CIRCUIT AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD protection device. The N-well area between the P+ doped regions, forms a base of the parasitic transistor. At some distance away from the P+ doped regions an N+ doped region is provided. The N-well in between the N+ doped region and base of the transistor forms a parasitic resistor of the ESD protection device. The N+ doped region and the emitter of the transistor are coupled to each other via an electrical connection. The ESD protection device has a limited snapback behaviour and has a well-tunable trigger voltage. | 08-06-2015 |
20150276815 | HIGH BANDWIDTH CURRENT SENSOR AND METHOD THEREFOR - A current sensor comprises a current carrying trace located within a substrate; and a sensing trace located within the substrate proximate to the current carrying trace; wherein the sensing trace detects an electromagnetic force (emf) generated by magnetic flux inductively coupled from the current carrying trace for transmitting to a current sensing device. | 10-01-2015 |
20150276847 | METHOD AND SYSTEM FOR TESTING A SEMICONDUCTOR DEVICE AGAINST ELECTROSTATIC DISCHARGE - A method of testing a semiconductor device against electrostatic discharge includes operating the semiconductor device, and, while operating the semiconductor device, monitoring a functional performance of the semiconductor device. The monitoring includes monitoring one or more signal waveforms of respective one or more signals on respective one or more pins of the semiconductor device to obtain one or more monitor waveforms, and monitoring one or more register values of one or more registers of the semiconductor device to obtain one or more monitor register values as function of time. The method includes applying an electrostatic discharge event to the semiconductor device while monitoring the functional performance of the semiconductor device. The method can further comprise determining a functional change from the one or more monitor waveforms and the one or more monitor register values as function of time. | 10-01-2015 |