Patent application number | Description | Published |
20140077355 | THREE-DIMENSIONAL SEMICONDUCTOR PACKAGE DEVICE HAVING ENHANCED SECURITY - A semiconductor package device that includes an integrated circuit device package having a storage circuitry is disclosed. In an implementation, the semiconductor package device includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes one or more integrated circuits formed proximal to (e.g., adjacent to, in, or on) the first surface. The semiconductor package device also includes an integrated circuit device disposed over the second surface, the integrated circuit device including storage circuitry for storing sensitive data. In one or more implementations, the semiconductor package device includes a through-substrate via that furnishes an electrical connection to the integrated circuit package. The semiconductor package device also includes an encapsulation structure disposed over the second surface and at least substantially encapsulates the integrated circuit device package. | 03-20-2014 |
20140077385 | SEMICONDUCTOR PACKAGE DEVICE HAVING PASSIVE ENERGY COMPONENTS - A semiconductor package device is disclosed that includes a passive energy component integrated therein. In an implementation, the semiconductor package device includes a semiconductor substrate having a first surface and a second surface. The semiconductor substrate includes one or more integrated circuits formed proximal to the first surface. The semiconductor package device also includes a passive energy component positioned over the second surface. The passive energy component is electrically connected to one or more integrated circuits. The semiconductor package device also includes an encapsulation structure disposed over the second surface and at least substantially encapsulates the passive energy component. | 03-20-2014 |
20140183747 | MULTI-DIE, HIGH CURRENT WAFER LEVEL PACKAGE - Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts. | 07-03-2014 |
20140231635 | MULTICHIP WAFER LEVEL PACKAGE (WLP) OPTICAL DEVICE - Optical devices are described that integrate multiple heterogeneous components in a single, compact package. In one or more implementations, the optical devices include a carrier substrate having a surface that includes two or more cavities formed therein. One or more optical component devices are disposed within the respective cavities in a predetermined arrangement. A cover is disposed on the surface of the carrier substrate so that the cover at least substantially encloses the optical component devices within their respective cavities. The cover, which may be glass, is configured to transmit light within the predetermined spectrum of wavelengths. | 08-21-2014 |
20140306337 | SEMICONDUCTOR DEVICE HAVING A BUFFER MATERIAL AND STIFFENER - Semiconductor devices are described that include a semiconductor device having multiple, stacked die on a substrate (e.g., a semiconductor wafer). In one or more implementations, wafer-level package devices that employ example techniques in accordance with the present disclosure include an ultra-thin semiconductor wafer with metallization and vias formed in the wafer and an oxide layer on the surface of the wafer, an integrated circuit chip placed on the semiconductor wafer, an underfill layer between the integrated circuit chip and the semiconductor wafer, a buffer material formed on the semiconductor wafer, the underfill layer, and at least one side of the integrated circuit chip, an adhesive layer placed on the buffer layer and the integrated circuit chip, and a stiffener layer placed on the adhesive layer. The semiconductor device may then be segmented into individual semiconductor chip packages. | 10-16-2014 |
20150255413 | ENHANCED BOARD LEVEL RELIABILITY FOR WAFER LEVEL PACKAGES - A wafer level package device, electronic device, and fabrication methods for fabrication of the wafer level package device are described that include forming an exposed lead tip on the wafer level package for providing a solder buttress structure when coupling the wafer level package device to another electrical component. In implementations, the wafer level package device includes at least one integrated circuit die, a metal pad, a first dielectric layer, a redistribution layer, a second dielectric layer, a pillar structure, a molding layer, a pillar layer, and a plating layer, where the pillar layer is sawn to form pad contacts on at least two sides of the wafer level package device. The exposed pad contact facilitate a solder fillet and buttress structure resulting in improved board level reliability. | 09-10-2015 |
20150279799 | WAFER LEVEL DEVICE AND METHOD WITH CANTILEVER PILLAR STRUCTURE - A wafer level package, electronic device including the wafer level package, and fabrication methods are described that include forming a cantilever pillar design as a portion of the wafer level package and/or a segmented solder connection for preventing and reducing connection stress and increasing board level reliability. In implementations, the wafer level device that employs example techniques in accordance with the present disclosure includes at least a section of a processed semiconductor wafer including at least one integrated circuit die, a first dielectric layer disposed on the processed semiconductor wafer, a first pillar, a second pillar formed on the first pillar, a second dielectric layer formed on the first dielectric layer and surrounding a portion of the first pillar and the second pillar, and at least one solder ball disposed on the second pillar. | 10-01-2015 |
20150325512 | MULTI-DIE, HIGH CURRENT WAFER LEVEL PACKAGE - Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts. | 11-12-2015 |