Pletka
Roman Pletka, Rueschlikon CH
Patent application number | Description | Published |
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20110138103 | INTRA-BLOCK MEMORY WEAR LEVELING - A method for intra-block wear leveling within solid-state memory subjected to wear, having a plurality of memory cells includes the step of writing to at least certain ones of the plurality of memory cells, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level. For example, if a behavior of at least some of the plurality of memory cells is not characterized, then the method may comprise characterizing a behavior of at least some of the plurality of memory cells and writing to at least certain ones of the plurality of memory cells, based on the characterized behavior, and in a non-uniform manner. | 06-09-2011 |
20120290899 | METHOD, DEVICE AND COMPUTER PROGRAM PRODUCT FOR DECODING A CODEWORD - A method and apparatus for decoding a codeword received from a flash memory. The flash memory comprises multi-level flash memory cells, wherein each multi-level flash memory cell stores one symbol of the codeword. An ECC decoder is arranged for decoding the codeword into a decoded codeword and correcting a maximum number of errors. The method determines the number of errors in the codeword. If the number of errors is more than the maximum number of errors that the ECC decoder can correct, the method generates modified codewords, calculates a corrective effect of a modified codeword, and determines a decoded codeword based on the corrective effect. | 11-15-2012 |
20130046930 | OPTIMIZING LOCATIONS OF DATA ACCESSED BY CLIENT APPLICATIONS INTERACTING WITH A STORAGE SYSTEM - A method for optimizing locations of physical data accessed by one or more client applications interacting with a storage system, with the storage system comprising at least two redundancy groups having physical memory spaces and data bands. Each of the data bands corresponds to physical data stored on several of the physical memory spaces. A virtualized logical address space includes client data addresses utilizable by the one or more client applications. A storage controller is configured to map the client data addresses onto the data bands, such that a mapping is obtained, wherein the one or more client applications can access physical data corresponding to the data bands. | 02-21-2013 |
20130046931 | OPTIMIZING LOCATIONS OF DATA ACCESSED BY CLIENT APPLICATIONS INTERACTING WITH A STORAGE SYSTEM - A method for optimizing locations of physical data accessed by one or more client applications interacting with a storage system, with the storage system comprising at least two redundancy groups having physical memory spaces and data bands. Each of the data bands corresponds to physical data stored on several of the physical memory spaces. A virtualized logical address space includes client data addresses utilizable by the one or more client applications. A storage controller is configured to map the client data addresses onto the data bands, such that a mapping is obtained, wherein the one or more client applications can access physical data corresponding to the data bands. | 02-21-2013 |
20130124794 | LOGICAL TO PHYSICAL ADDRESS MAPPING IN STORAGE SYSTEMS COMPRISING SOLID STATE MEMORY DEVICES - The present idea provides a high read and write performance from/to a solid state memory device. The main memory of the controller is not blocked by a complete address mapping table covering the entire memory device. Instead such table is stored in the memory device itself, and only selected portions of address mapping information are buffered in the main memory in a read cache and a write cache. A separation of the read cache from the write cache enables an address mapping entry being evictable from the read cache without the need to update the related flash memory page storing such entry in the flash memory device. By this design, the read cache may advantageously be stored on a DRAM even without power down protection, while the write cache may preferably be implemented in nonvolatile or other fail-safe memory. This leads to a reduction of the overall provisioning of nonvolatile or fail-safe memory and to an improved scalability and performance. | 05-16-2013 |
20130166827 | WEAR-LEVEL OF CELLS/PAGES/SUB-PAGES/BLOCKS OF A MEMORY - The invention is directed to a method for wear-leveling cells or pages or sub-pages or blocks of a memory such as a flash memory, the method comprising:—receiving (S | 06-27-2013 |
20130346538 | MANAGING CACHE MEMORIES - A method for managing cache memories includes providing a computerized system including a shared data storage system (CS) configured to interact with several local servers that serve applications using respective cache memories, and access data stored in the shared data storage system; providing cache data information from each of the local servers to the shared data storage system, the cache data information comprising cache hit data representative of cache hits of each of the local servers, and cache miss data representative of cache misses of each of the local servers; aggregating, at the shared data storage system, at least part of the cache hit and miss data received and providing the aggregated cache data information to one or more of the local servers; and at the local servers, updating respective one or more cache memories used to serve respective one or more applications based on the aggregated cache data information. | 12-26-2013 |
Roman Pletka, Zurich CH
Patent application number | Description | Published |
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20120131265 | WRITE CACHE STRUCTURE IN A STORAGE SYSTEM - A method of writing data units to a storage device. The data units are cached in a first level cache sorted by logical address. A group (G | 05-24-2012 |
20130138912 | SCHEDULING REQUESTS IN A SOLID STATE MEMORY DEVICE - An apparatus and method for a memory controller for managing scheduling requests in a solid state memory device. The memory includes a set of units wherein a unit within the set of units is erasable as a whole by a unit reclaiming process resulting in a free unit available for writing data to. The memory controller further includes a first queue for queuing user requests for reading and/or writing data from/to the memory, and a second queue for queuing unit reclaiming requests for executing the unit reclaiming process. A scheduler is provided for selecting user requests from the first queue and unit reclaiming requests from the second queue for execution according to a defined ratio. The defined ratio is a variable ratio, is dependent on the current number of free units, and permits the memory controller to select requests from both the first queue and the second queue. | 05-30-2013 |
20130159609 | PROCESSING UNIT RECLAIMING REQUESTS IN A SOLID STATE MEMORY DEVICE - An apparatus and method for processing unit reclaiming requests in a solid state memory device. The present invention provides a method of managing a memory which includes a set of units. The method includes selecting a unit from the set of units having plurality of subunits. The method further includes determining a number of valid subunits m to be relocated from the units selected for a batch operation where m is at least 2. The selecting is carried out by a unit reclaiming process. | 06-20-2013 |
Roman Pletka, Uster CH
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20120303860 | Method and Controller for Identifying a Unit in a Solid State Memory Device for Writing Data To - In a method for identifying a unit in a solid state memory device for writing data to a tier structure is maintained the tier structure comprising at least two tiers for assigning units available for writing data to. In response to receiving a request for writing data it is determined if a unit for writing data to is available in a first tier of the at least two tiers. In response to determining that a unit is available for writing data to in the first tier this unit is identified for writing data to, and in response to determining that no unit is available for writing the data to in the first tier it is determined if a unit is available for writing data to in a second tier of the at least two tiers subject to a priority of the write request. | 11-29-2012 |
20120303878 | Method and Controller for Identifying a Unit in a Solid State Memory Device for Writing Data to - In a method for identifying a unit in a solid state memory device for writing data to a tier structure is maintained the tier structure comprising at least two tiers for assigning units available for writing data to. In response to receiving a request for writing data it is determined if a unit for writing data to is available in a first tier of the at least two tiers. In response to determining that a unit is available for writing data to in the first tier this unit is identified for writing data to, and in response to determining that no unit is available for writing the data to in the first tier it is determined if a unit is available for writing data to in a second tier of the at least two tiers subject to a priority of the write request. | 11-29-2012 |
20150067271 | SELECTIVELY ENABLING WRITE CACHING IN A STORAGE SYSTEM BASED ON PERFORMANCE METRICS - According to a method of cache management in a data storage system including a write cache and bulk storage media, a storage controller of the data storage system caches, in the write cache, write data of write input/output operations (IOPs) received at the storage controller. In response to a first performance-related metric for the data storage system satisfying a first threshold, the storage controller decreases a percentage of write IOPs for which write data is cached in the write cache of the data storage system and increases a percentage of write IOPs for which write data is stored directly in the bulk storage media in lieu of the write cache. In response to a second performance-related metric for the data storage system satisfying a second threshold, the storage controller increases the percentage of write IOPs for which write data is cached in the write cache of the data storage system. | 03-05-2015 |
Roman A. Pletka, Zurich CH
Patent application number | Description | Published |
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20150154061 | PAGE RETIREMENT IN A NAND FLASH MEMORY SYSTEM - In a data storage system including a non-volatile random access memory (NVRAM) array, a page is a smallest granularity of the NVRAM array that can be accessed by read and write operations, and a memory block containing multiple pages is a smallest granularity of the NVRAM array that can be erased. Data are stored in the NVRAM array in page stripes distributed across multiple memory blocks. In response to detection of an error in a particular page of a particular block of the NVRAM array, only the particular page of the particular block is retired, such that at least two of the multiple memory blocks across which a particular one of the page stripes is distributed include differing numbers of active (non-retired) pages. | 06-04-2015 |