Prabhakar, CA
Abhiram Prabhakar, Fremont, CA US
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20080320374 | METHOD AND APPARATUS FOR DECODING A LDPC CODE - In a decoder having a predetermined decoder structure for decoding a low density parity check (LDPC) code suitable for decoding multi-rated LDPC codes is provided. An associated method is provided. The method comprises the steps of: providing a memory for the decoding with the memory size proportional to the number of circularly shifted-identity matrices I (t); and providing a number M for both row update unit numbers and column-update unit numbers. Whereby an improved architecture having an improved logic and the memory is provided such that an improved throughput, power consumption, and memory area are achieved. | 12-25-2008 |
20090070659 | LDPC DECODER WITH AN IMPROVED LLR UPDATE METHOD USING A SET OF RELATIVE VALUES FREE FROM A SHIFTING ACTION - In a decoder having an improved LLR (log-likelihood-ratio) update method is provided. The method comprising the steps of: providing a parity check matrix; and using merely a set of parameters on a row of the parity check matrix instead of data of the whole non-zero elements of the parity check matrix free from at least one shifting action after each row updating; thereby saving memory space and process time. | 03-12-2009 |
20090282313 | METHOD AND APPARATUS FOR HARD DECISION BOUNDED DISTANCE DECODING OF NORDSTROM ROBINSON CODE - A receiver is provided that comprises a decoder. The decoder comprises: means for slicing a signal; means for encoding data/messages to a code word among a predetermined number of code words; and means for determining a distance associated with the code word. | 11-12-2009 |
Abhiram Prabhakar, Pleasonton, CA US
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20080276151 | METHOD AND APPARATUS FOR DECODING A LDPC CODE - In a decoder for decoding a low density parity check (LDPC) code suitable for decoding multi-rated LDPC codes, a method is provided. The method comprises the steps of: providing a memory for the decoding with the memory dependent on a parity check matrix H with maximum number of “1”s; using a number of column updating units, updating columns parallely and simultaneously producing messages; and using a number of row updating units, updating rows parallely and simultaneously producing messages. Whereby an improved architecture in a logic and the memory is provided such that an improved throughput, power consumption, and memory area is achieved. | 11-06-2008 |
Aditya Prabhakar, San Mateo, CA US
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20160058188 | SYSTEMS AND METHODS FOR DAMPING A STORAGE SYSTEM - In an embodiment, an apparatus (e.g., for damping a motion of a drawer in a storage system) comprises a plate to pivotally attach to a first wall of a drawer, the plate comprising a pivot point about which the plate can pivot; a damped gear coupled to the plate, the damped gear having a plurality of gear teeth; and a spring to facilitate pivoting the plate about the pivot point to engage at least one of the plurality of gear teeth with at least one tooth on a rack. In some embodiments, the spring is to pivot the plate from a first configuration to an angular position relative the wall in a second configuration, wherein the at least one of the plurality of gear teeth and the at least one tooth on the rack are fully engaged with one another in both the first configuration and the second configuration. | 03-03-2016 |
Balaji Prabhakar, Palo Alto, CA US
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20090113069 | APPARATUS AND METHOD FOR PROVIDING A CONGESTION MEASUREMENT IN A NETWORK - Example embodiments of a system and method for providing a congestion measurement in a network are disclosed. In an example embodiment information is received at an information transfer rate, from a source network device. A sample of the information may be taken before the information is transmitted to a destination network device. In an example embodiment, a congestion measurement value is computed that corresponds to the sample and represented with at least two bits. A multi-bit indicator of the congestion measurement value is then transmitted to control the information transfer rate of information arriving in the future. | 04-30-2009 |
20090238070 | METHOD AND SYSTEM TO ADJUST CN CONTROL LOOP PARAMETERS AT A CONGESTION POINT - A method and system to adjust Congestion Notification control loop parameters at a congestion point are provided. The system comprises a monitor to sample a state of a congestion point the congestion point being to receive messages from a reaction point; a history generator to generate an updated reaction to congestion history by consolidating the state of the congestion point with a current reaction to congestion history, the current reaction to congestion history being associated with a current feedback message; a message generator to generate an updated feedback message based on the updated reaction to congestion history; a message update module to replace the current feedback message with the updated feedback message; and a communications module to communicate the updated feedback message to the reaction point. | 09-24-2009 |
20100157803 | METHOD AND SYSTEM TO MANAGE NETWORK TRAFFIC CONGESTION IN NETWORKS WITH LINK LAYER FLOW CONTROL - A method and system to manage network traffic congestion in networks with link layer flow control is provided. The system comprises a physical queue monitor configured to monitor a state of a physical queue at a network device, a link layer flow control activator configured to activate link layer flow control based on the state of the physical queue, a proxy queue control module, a proxy queue monitor to monitor the state of the proxy queue, and a transport layer flow control activator. The proxy queue control module may be configured to update a state of a proxy queue based on the state of the physical queue. The proxy queue monitor may be configured to monitor the state of the proxy queue. The transport layer flow control activator may be configured to activate transport layer flow control based on the state of the proxy queue. | 06-24-2010 |
20100198671 | RECYCLING REWARD SYSTEM AND METHOD THEREOF - Systems and methods are provided for incentivizing and rewarding consistent and repeated recycling of recyclable materials. | 08-05-2010 |
20100302941 | METHOD AND SYSTEM TO MANAGE NETWORK TRAFFIC CONGESTION - A method and system to manage network congestion are provided. In one example embodiment, the method comprises receiving an indication of a rate increase request at a reaction point computer system, determining information indicative of a frequency of rate decrease requests during a period of time, and initiating a rate increase signal utilizing the information indicative of the frequency of rate decrease requests during the period of time. | 12-02-2010 |
20110211449 | COMMUNICATION TRANSPORT OPTIMIZED FOR DATA CENTER ENVIRONMENT - Methods and apparatus for congestion control in computer networks achieve high burst tolerance, low latency and high throughput with shallow-buffered switches. A method for controlling congestion includes transmitting a set of data packets on a network connection from a first computing device to a second computing device, identifying each data packet in the set of data packets that experienced congestion on the network connection, sending, by the second computing device to the first computing device, a sequence of bits that represents the number of data packets in the set of data packets that were identified as having experienced congestion, and adjusting a rate of transmitting data packets on the network connection based on the sequence of bits sent to the first computing device. | 09-01-2011 |
20130227163 | APPARATUS AND METHOD FOR PROVIDING A CONGESTION MEASUREMENT IN A NETWORK - Example embodiments of a system and method for providing a congestion measurement in a network are disclosed. In an example embodiment information is received at an information transfer rate, from a source network device. A sample of the information may be taken before the information is transmitted to a destination network device. In an example embodiment, a congestion measurement value is computed that corresponds to the sample and represented with at least two bits. A multi-bit indicator of the congestion measurement value is then transmitted to control the information transfer rate of information arriving in the future. | 08-29-2013 |
Balaji S. Prabhakar, Palo Alto, CA US
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20100226384 | Method for reliable transport in data networks - Rapid and reliable network data delivery uses state sharing to combine multiple flows into one meta-flow at an intermediate network stack meta-layer, or shim layer. Copies of all packets of the meta-flow are buffered using a common wait queue having an associated retransmit timer, or set of timers. The timers may have fixed or dynamic timeout values. The meta-flow may combine multiple distinct data flows to multiple distinct destinations and/or from multiple distinct sources. In some cases, only a subset of all packets of the meta-flow are buffered. | 09-09-2010 |
20120226532 | MITIGATION OF CONGESTION IN USE OF A CAPACITY CONSTRAINED RESOURCE BY PROVIDING INCENTIVES - Congestion of a network being accessed by users is mitigated by providing predetermined incentive credits to users who follow network use recommendations and allowing the users to redeem accumulated credits for entry in a game of chance that provides a chance of winning a large reward. A server collects network use data to determine network congestion states and to determine whether users followed network use recommendations. The server also implements a web portal through which users can view historical network use and awarded credits, and redeem their credits. Application domains of the method to mitigate congestion include public transportation networks, wireless communication networks, and energy distribution networks. The techniques may also be enhanced by integration with online social networking features. | 09-06-2012 |
20120284096 | Resource Usage Reduction via Incentives - Conservation of a utility resource is incentivized by a method in which a utility customer records utility meter readings with a smart phone and submits the readings to a server for processing. The server processes the meter readings and awards the customer with credit awards contingent upon customer compliance with behavior that is being incentivized by the system, e.g., reduced resource use during peak hours, resource use below a target level set by the server, resource use below a goal set by the customer, frequent and accurate resource meter submissions, or verification of resource submissions of other customers. Cumulative awarded credits may be redeemed by a customer in exchange for participation in a micro-raffle or other game of chance. Preferably, a consumer awarded more credits has a greater chance of winning a prize, and a greater chance of winning a larger prize, than a user awarded fewer credits. | 11-08-2012 |
Balaji Satyanarayana Prabhakar, Palo Alto, CA US
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20150177011 | TRANSPORTATION SYSTEM RECONSTRUCTION - A system for reconstructing vehicle itinerary include a processor and a memory storing instructions, implemented by the processor, to cluster historical trip records into a plurality of clusters, each of the plurality of clusters including a set of historical trip records that describe events occurring within a predetermined time range at one location; identify a sequence of clusters that includes a cluster at each location; and estimate an itinerary for a vehicle based on the sequence of clusters and constraint data describing physical constraints, the itinerary for the vehicle describing a sequence of arrival and departure times at a sequence of locations for the vehicle. | 06-25-2015 |
Kal Prabhakar, San Jose, CA US
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20110030055 | Detecting Spoofing in Wireless Digital Networks - Detecting spoofing in a digital network. Packets of information in a digital network using a shared medium contain a unique identifier for the device originating the packet. An individual device may be transmitting, or receiving, but not both. If a device receives a packet containing its unique identifier as the origin address, that packet must have been transmitted by another device, and a spoofing alert is raised. | 02-03-2011 |
20110107417 | Detecting AP MAC Spoofing - Detecting access point MAC spoofing in a wireless digital network. A sensor in a wireless digital network learns the MAC address and operating channel for at least one access point. If the sensor detects frames being sent to a MAC address on a channel other than the channel associated with that MAC address, then the access point associated with the MAC address is being spoofed. These frames may be association frames, or data frames. If the sensor is running as part of an access point the sensor also knows what clients are associated with the access point. If the sensor detects frames indicating association, such as data frames, sent to its MAC address, but the client is not associated with the access point, then the access point is being spoofed. Similarly, if the sensor receives frames on a channel other than that associated with the access point and receives traffic for the access point's MAC address, the access point is being spoofed. The sensor may be a separate device on the wireless network, or may be functionality included in one or more access points on the network. | 05-05-2011 |
Kiran Prabhakar, Cupertino, CA US
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20140280819 | THROTTLING GROUP IN ORACLE SERVICE BUS - A computer-controlled method can include creating a throttling group corresponding to a backend server configured to provide business services to multiple electronic devices over a service bus, defining a throttling group parameter for the throttling group, and routing messages based on the throttling group parameter. | 09-18-2014 |
Krishna Prabhakar, Los Altos, CA US
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20130042002 | METHOD AND APPARATUS FOR POLICY-BASED NETWORK ACCESS CONTROL WITH ARBITRARY NETWORK ACCESS CONTROL FRAMEWORKS - A method and apparatus for integrating various network access control frameworks under the control of a single policy decision point (PDP). The apparatus supports pluggable protocol terminators to interface to any number of access protocols or backend support services. The apparatus contains Trust and Identity Mediators to mediate between the protocol terminators and a canonical policy subsystem, translating attributes between framework representations, and a canonical representation using extensible data-driven dictionaries. | 02-14-2013 |
Krishna Prabhakar, Los Altos Hills, CA US
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20140237543 | METHOD AND APPARATUS FOR POLICY-BASED NETWORK ACCESS CONTROL WITH ARBITRARY NETWORK ACCESS CONTROL FRAMEWORKS - A method and apparatus for integrating various network access control frameworks under the control of a single policy decision point (PDP). The apparatus supports pluggable protocol terminators to interface to any number of access protocols or backend support services. The apparatus contains Trust and Identity Mediators to mediate between the protocol terminators and a canonical policy subsystem, translating attributes between framework representations, and a canonical representation using extensible data-driven dictionaries. | 08-21-2014 |
20160070712 | Dynamically Modifying Geographical Search Regions - A first search is executed to obtain a first set of search results corresponding to a first geographical search area. A determination is made that the first set of search results does not meet a search results criteria. A second geographical search region is dynamically selected for executing a second search in response to determining that the first set of search results does not meet the search results criteria. The second search is executed to obtain a second set of search results corresponding to the second geographical search area. | 03-10-2016 |
Ram Prabhakar, Palo Alto, CA US
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20080225957 | Dynamic packet size control for MPEG-4 data partition mode - A dynamic AC prediction technique is implemented in a data partition mode which automatically disables AC prediction for encoding the current macroblock in the next packet when packet overflow occurs. Otherwise, when there is no overflow, AC prediction remains enabled to maintain compression efficiency. More particularly, in the preferred embodiment, a determination is first made whether a macroblock causes a packet overflow if it is encoded in the current packet. If so, a new packet is initiated into which the macroblock is encoded without AC prediction as the first macroblock. Otherwise, the macroblock with AC prediction remains in the current packet and a new macroblock is encoded. | 09-18-2008 |
20100106918 | VARIABLE-LENGTH CODING DATA TRANSFER INTERFACE - A VLC data transfer interface is presented that allows digital data to be packed and assembled according to a format selectable from a number of formats while the data is being transferred to a desired destination. | 04-29-2010 |
Salil Prabhakar, Fremont, CA US
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20140307077 | APPARATUSES AND METHODS FOR IRIS IMAGING - The invention includes a method and apparatus for acquiring an image of a subject's iris, within the near infrared region of the electromagnetic spectrum. Near infrared radiation is generated from an incandescent light source, having wavelengths spread across 700 nm to 900 nm. The iris is illuminated for imaging by directing the generated near infrared radiation along an optical path between the incandescent light source and an intersection of a field of view region and depth of field region of an iris camera. Near infrared radiation scattered by the iris and transmitted along the iris camera's optical axis is received at the iris camera. An image of the iris is then acquired at the iris camera, based on radiation scattered by the iris and received at the iris camera. | 10-16-2014 |
20140327753 | APPARATUS AND METHOD FOR POSITIONING AN IRIS FOR IRIS IMAGE CAPTURE - The invention provides an apparatus and method for positioning an iris for iris image capture. An iris image sensor is configured to have an image capture region defining an intended position of the subject's iris for image capture. An optical system comprising a reflective element is disposed such that, responsive to positioning of the subject's iris within the image capture region, the optical system forms a subject viewable in-focus upright image of the subject's iris. The optical system may be configured such that length of an optical path between the intended position of the subject's iris during image capture and the reflective element is less than half of a near point distance. The optical system may be further configured such that a distance between the image capture region and the in-focus upright image formed by the optical system is greater than or equal to the near point distance. | 11-06-2014 |
20140327754 | METHOD AND APPARATUS FOR COMPENSATING FOR SUB-OPTIMAL ORIENTATION OF AN IRIS IMAGING APPARATUS - The invention comprises a method and apparatus for compensating for sub-optimal orientation of an iris imaging apparatus during image capture. The iris imaging apparatus of the invention comprises an iris camera and a deviation sensor. The deviation sensor may be configured to detect deviations between a current orientation of the iris camera and a predetermined optimal orientation for the iris camera. Responsive to a detected deviation a correction is effected to compensate for the detected deviation. | 11-06-2014 |
20140327755 | APPARATUS AND METHOD FOR POSITIONING AN IRIS FOR IRIS IMAGE CAPTURE - The invention provides an apparatus and method for positioning an iris for iris image capture. An iris image sensor is configured to have an image capture region defining an intended position of the subject's iris for image capture. A feedback object and an optical system are provided. In one aspect, the optical system may comprise a lens element disposed such that, responsive to positioning of the subject's iris within the image capture region, the optical system forms a subject viewable in-focus upright image of the feedback object. In another aspect, the optical system may comprise an occluder, configured such that responsive to positioning of the subject's iris partially or wholly outside the image capture region, the optical system occludes at least a portion of the feedback object from the subject's view. | 11-06-2014 |
20150071503 | APPARATUSES AND METHODS FOR IRIS BASED BIOMETRIC RECOGNITION - The invention provides a method for iris based biometric recognition. The method includes receiving an image from an image sensor and determining whether the received image includes an iris. The steps of receiving and determining are repeated until the received image includes an iris. Responsive to determining that a received image includes an iris, iris information corresponding to such received image is compared with stored iris information corresponding to at least one iris and a match decision or a non-match decision is rendered based on an output of the comparison. The invention additionally provides a system and computer program product configured for iris based biometric recognition. | 03-12-2015 |
20150362700 | IRIS IMAGING APPARATUS AND METHODS FOR CONFIGURING AN IRIS IMAGING APPARATUS - The invention comprises an iris imaging apparatus comprising an image sensor and an optical assembly. The optical assembly comprises an image-side surface and an object-side surface. The optical imaging lens assembly may be configured such that D1≦6 mm, PX | 12-17-2015 |
Swetha Prabhakar, Los Altos Hills, CA US
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20160070712 | Dynamically Modifying Geographical Search Regions - A first search is executed to obtain a first set of search results corresponding to a first geographical search area. A determination is made that the first set of search results does not meet a search results criteria. A second geographical search region is dynamically selected for executing a second search in response to determining that the first set of search results does not meet the search results criteria. The second search is executed to obtain a second set of search results corresponding to the second geographical search area. | 03-10-2016 |
Venkatraman Prabhakar, Pleasanton, CA US
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20080225601 | EEPROM MEMORY DEVICE WITH CELL HAVING NMOS IN A P POCKET AS A CONTROL GATE, PMOS PROGRAM/ERASE TRANSISTOR, AND PMOS ACCESS TRANSISTOR IN A COMMON WELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 09-18-2008 |
20080273392 | METHOD OF PROGRAMMING A SELECTED MEMORY CELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 11-06-2008 |
20080273401 | METHOD OF ERASING A BLOCK OF MEMORY CELLS - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 11-06-2008 |
20090014772 | EEPROM MEMORY CELL WITH FIRST-DOPANT-TYPE CONTROL GATE TRANSISTOR, AND SECOND-DOPANT TYPE PROGRAM/ERASE AND ACCESS TRANSISTORS FORMED IN COMMON WELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 01-15-2009 |
20110089420 | BACKSIDE ONLY CONTACT THIN-FILM SOLAR CELLS AND DEVICES, SYSTEMS AND METHODS OF FABRICATING SAME, AND PRODUCTS PRODUCED BY PROCESSES THEREOF - Systems, methods, devices, and products of processes consistent with the innovations herein relate to thin-film solar cells having contacts on the backside, only. In one exemplary implementation, there is provided a thin film device. Moreover, such device may comprise a substrate, and a layer of silicon or silicon-containing material positioned on a first side of the substrate, wherein the layer comprises a n-doped region and a p-doped region. In some exemplary implementations, the device may be fabricated such that the n-doped region and the p-doped region are formed on the backside surface of the layer to create an electrical structure characterized by a P-type anode and an N-type cathode forming a junction positioned along the backside surface of the layer. | 04-21-2011 |
20110089429 | SYSTEMS, METHODS AND MATERIALS INVOLVING CRYSTALLIZATION OF SUBSTRATES USING A SEED LAYER, AS WELL AS PRODUCTS PRODUCED BY SUCH PROCESSES - Systems, methods, and products of processes consistent with the innovations herein relate to aspects involving crystallization of layers on substrates. In one exemplary implementation, there is provided a method of fabricating a device. Moreover, such method may include placing a seed layer on a base substrate, covering the seed layer with an amorphous/poly material, and heating the seed layer/material to transform the material into crystalline form. | 04-21-2011 |
20110101364 | SYSTEMS, METHODS AND MATERIALS INCLUDING CRYSTALLIZATION OF SUBSTRATES VIA SUB-MELT LASER ANNEAL, AS WELL AS PRODUCTS PRODUCED BY SUCH PROCESSES - Systems, methods, and products of processes consistent with the innovations herein relate to aspects involving crystallization of layers on substrates. In one exemplary implementation, there is provided a method of fabricating a device. Moreover, such method may include placing an amorphous/poly material on a substrate and heating the material via a sub-melt laser anneal process to transform the material into crystalline form. | 05-05-2011 |
20110165721 | SYSTEMS, METHODS AND PRODUCTS INCLUDING FEATURES OF LASER IRRADIATION AND/OR CLEAVING OF SILICON WITH OTHER SUBSTRATES OR LAYERS - The present innovations relate to optical/electronic structures, and, more particularly, to methods and products consistent with composite structures for optical/electronic applications, such as solar cells and displays, composed of a silicon-containing material bonded to a substrate and including laser treatment. | 07-07-2011 |
20110306180 | Systems, Methods and Products Involving Aspects of Laser Irradiation, Cleaving, and/or Bonding Silicon-Containing Material to Substrates - Systems, methods and products by process are disclosed relating to structures and/or fabrication thereof as relating, for example, to optical/electronic applications such as solar cells and displays. In one exemplary implementation, there is provided a method of producing a composite structure. Moreover, the method may include engaging a silicon-containing material into contact with a surface of the substrate and irradiating/treating the silicon-containing piece with a laser. | 12-15-2011 |
20120018733 | Thin Film Solar Cells And Other Devices, Systems And Methods Of Fabricating Same, And Products Produced By Processes Thereof - Systems, methods, devices, and products of processes consistent with the innovations herein relate to thin-film solar cells and other devices. In one exemplary implementation, there is provided a thin film device. | 01-26-2012 |
20130083608 | 1T SMART WRITE - The threshold voltages of particular nonvolatile memory cells on a word line are selectively increased on a column by column (cell by cell) basis. A selective program is performed on some of the cells, and simultaneously a program inhibit on other of the cells, resulting in all of the cells having a threshold voltage that falls between a minimum acceptable value and a maximum acceptable value. | 04-04-2013 |
20130122629 | SYSTEMS, METHODS AND PRODUCTS INCLUDING FEATURES OF LASER IRRADIATION AND/OR CLEAVING OF SILICON WITH OTHER SUBSTRATES OR LAYERS - The present innovations relate to optical/electronic structures, and, more particularly, to methods and products consistent with composite structures for optical/electronic applications, such as solar cells and displays, composed of a silicon-containing material bonded to a substrate and including laser treatment. | 05-16-2013 |
20140021477 | SYSTEMS, METHODS AND MATERIALS INCLUDING CRYSTALLIZATION OF SUBSTRATES VIA SUB-MELT LASER ANNEAL, AS WELL AS PRODUCTS PRODUCED BY SUCH PROCESSES - Systems, methods, and products of processes consistent with the innovations herein relate to aspects involving crystallization of layers on substrates. In one exemplary implementation, there is provided a method of fabricating a device. Moreover, such method may include placing an amorphous/poly material on a substrate and heating the material via a sub-melt laser anneal process to transform the material into crystalline form. | 01-23-2014 |
20140197864 | Non-Volatile Latch Structures with Small Area for FPGA - A latch circuit and method includes providing a first tri-gate non-volatile device, providing a second tri-gate non-volatile device, coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device, erasing the first tri-gate non-volatile device, programming the second tri-gate non-volatile device, and latching an output node of the latch device to a logic state determined by respective thresholds of the first and second tri-gate non-volatile devices. Coupling the first tri-gate non-volatile device to the second tri-gate non-volatile device can include direct coupling, or indirect coupling through a cross-coupled circuit. | 07-17-2014 |
20140239374 | EMBEDDED SONOS BASED MEMORY CELLS - Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric on the substrate and a charge-trapping layer on the tunneling dielectric; patterning the dielectric stack to form a gate stack of a NVM transistor of a memory device in a first region of the substrate while concurrently removing the dielectric stack from a second region of the substrate; and performing a gate oxidation process of a baseline CMOS process flow to thermally grow a gate oxide of a MOS transistor overlying the substrate in the second region while concurrently growing a blocking oxide overlying the charge-trapping layer. In one embodiment, Indium is implanted to form a channel of the NVM transistor. | 08-28-2014 |
20140264552 | NONVOLATILE MEMORY CELLS AND METHODS OF MAKING SUCH CELLS - A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel. Methods of forming such a memory cell are also disclosed. | 09-18-2014 |
20140301139 | Method to Reduce Program Disturbs in Non-Volatile Memory Cells - A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (V | 10-09-2014 |
20150041881 | Embedded SONOS Based Memory Cells - A memory device that includes a non-volatile memory (NVM) transistor which has an indium doped channel and a gate stack overlying the channel formed in a first region of a substrate and a metal-oxide-semiconductor (MOS) transistor formed in a second region of the substrate in which the gate oxide of the MOS and the oxide layer of the NVM transistor are formed concurrently. | 02-12-2015 |
20150200295 | Drain Extended MOS Transistors With Split Channel - A circuit including both drain-extended metal-oxide-semiconductor (DEMOS) and low-voltage metal-oxide-semiconductor (LV_MOS) devices and methods of manufacturing the same are provided. In one embodiment, DEMOS device includes a first channel, a gate, a second channel, and a drain extension, wherein the second channel is split into a first portion and a second portion, and wherein the first portion of the second channel stops under the gate and is spaced away from the drain extension. Other embodiments are also described. | 07-16-2015 |
20150287464 | SYSTEMS, METHODS, AND APPARATUS FOR MEMORY CELLS WITH COMMON SOURCE LINES - Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor. | 10-08-2015 |
20150287811 | Methods to integrate SONOS into CMOS Flow - A method of forming a transistor is described. In one embodiment the method includes: forming a channel of a transistor in a surface of a substrate; forming a dielectric stack including a first oxide layer overlying the surface of the substrate, a middle layer comprising nitride overlying the first oxide layer and a second oxide layer overlying the middle layer; forming over the dielectric stack a mask exposing source and drain (S/D) regions of the transistor; etching the dielectric stack through the mask to thin the dielectric stack by removing the second oxide layer and at least a first portion of the middle layer in S/D regions of the transistor; and implanting dopants into S/D regions of the transistor through the thinned dielectric stack to form a lightly-doped drain (LDD) adjacent to the channel of the transistor. Other embodiments are also described. | 10-08-2015 |
20150294731 | Method to Reduce Program Disturbs in Non-Volatile Memory Cells - A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (V | 10-15-2015 |
Vinay Prabhakar, Cupertino, CA US
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20130115764 | SUBSTRATE PROCESSING SYSTEM AND METHOD - A system for processing substrates has a vacuum enclosure and a processing chamber situated to process wafers in a processing zone inside the vacuum enclosure. Two rail assemblies are provided, one on each side of the processing zone. Two chuck arrays ride, each on one of the rail assemblies, such that each is cantilevered on one rail assemblies and support a plurality of chucks. The rail assemblies are coupled to an elevation mechanism that places the rails in upper position for processing and at lower position for returning the chuck assemblies for loading new wafers. A pickup head assembly loads wafers from a conveyor onto the chuck assemblies. The pickup head has plurality of electrostatic chucks that pick up the wafers from the front side of the wafers. Cooling channels in the processing chucks are used to create air cushion to assist in aligning the wafers when delivered by the pickup head. | 05-09-2013 |
20140170795 | GRID FOR PLASMA ION IMPLANT - A grid for minimizing effects of ion divergence in plasma ion implant. The plasma grid is made of a flat plate having a plurality of holes, wherein the holes are arranged in a plurality of rows and a plurality of columns thereby forming beamlets of ions that diverge in one direction. A mask is used to form the implanted shapes on the wafer, wherein the holes in the mask are oriented orthogonally to the direction of beamlet divergence. | 06-19-2014 |
20160042913 | IMPLANT MASKING AND ALIGNMENT - System and method to align a substrate under a shadow mask. A substrate holder has alignment mechanism, such as rollers, that is made to abut against an alignment straight edge. The substrate is then aligned with respect to the straight edge and is chucked to the substrate holder. The substrate holder is then transported into a vacuum processing chamber, wherein it is made to abut against a mask straight edge to which the shadow mask is attached and aligned to. Since the substrate was aligned to an alignment straight edge, and since the mask is aligned to the mask straight edge that is precisely aligned to the alignment straight edge, the substrate is perfectly aligned to the mask. | 02-11-2016 |
Vinay Prabhakar, Fremont, CA US
Patent application number | Description | Published |
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20100155254 | WAFER ELECTROPLATING APPARATUS FOR REDUCING EDGE DEFECTS - Methods, apparatuses, and various apparatus components, such as base plates, lipseals, and contact ring assemblies are provided for reducing contamination of the contact area in the apparatuses. Contamination may happen during removal of semiconductor wafers from apparatuses after the electroplating process. In certain embodiments, a base plate with a hydrophobic coating, such as polyamide-imide (PAI) and sometimes polytetrafluoroethylene (PTFE), are used. Further, contact tips of the contact ring assembly may be positioned further away from the sealing lip of the lipseal. In certain embodiments, a portion of the contact ring assembly and/or the lipseal also include hydrophobic coatings. | 06-24-2010 |
20120181170 | WAFER ELECTROPLATING APPARATUS FOR REDUCING EDGE DEFECTS - Methods, apparatuses, and various apparatus components, such as base plates, lipseals, and contact ring assemblies are provided for reducing contamination of the contact area in the apparatuses. Contamination may happen during removal of semiconductor wafers from apparatuses after the electroplating process. In certain embodiments, a base plate with a hydrophobic coating, such as polyamide-imide (PAI) and sometimes polytetrafluoroethylene (PTFE), are used. Further, contact tips of the contact ring assembly may be positioned further away from the sealing lip of the lipseal. In certain embodiments, a portion of the contact ring assembly and/or the lipseal also include hydrophobic coatings. | 07-19-2012 |