Qadeer
Mohammed Abdul Qadeer, Lewisville, NC US
Patent application number | Description | Published |
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20120209318 | NATURAL ORIFICE TRANSLUMINAL ENDOSCOPIC DEVICES FOR CLOSURE OF LUMINAL PERFORATIONS AND ASSOCIATED METHODS - Devices include at least two spaced apart flexible legs formed of a shape memory material, each leg having a respective free end configured to engage local tissue. The devices can also include at least one resilient member having opposing end portions, a respective end portion being attached to each leg at a location away from the free end. The resilient member is configured to take on a stretched configuration inside an endoscope during delivery. Alternatively or additionally, the devices include a cinch that is configured to snugly hold portions of both legs to force the legs closer together. | 08-16-2012 |
20120226287 | ENDOSCOPIC DEVICES FOR TISSUE REMOVAL OR REPAIR AND ASSOCIATED METHODS - Endoscopic medical devices for removing tissue include: (a) a forceps with an elongate shaft slidably residing in a first working channel of an endoscope and having an externally accessible forceps control; and (b) a snare with an elongate shaft comprising a wire loop slidably residing in the first working channel of the endoscope, the snare having an externally accessible snare control. The forceps and snare shafts reside adjacent to and substantially parallel to each other inside the first working channel of the endoscope, one above or to the side of the other. In use, the forceps and snare cooperate so that the forceps control directs the forceps to extend out of the endoscopic first working channel and grasp target tissue, then the snare control directs the snare loop to exit the working channel while the snare loop encircles the forceps shaft and extends a distance sufficient to surround the forceps. | 09-06-2012 |
Mohammed Abdul Qadeer, Northfield, IL US
Patent application number | Description | Published |
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20150257758 | NATURAL ORIFICE TRANSLUMINAL ENDOSCOPIC DEVICES FOR CLOSURE OF LUMINAL PERFORATIONS AND ASSOCIATED METHODS - Devices include at least two spaced apart flexible legs formed of a shape memory material, each leg having a respective free end configured to engage local tissue. The devices can also include at least one resilient member having opposing end portions, a respective end portion being attached to each leg at a location away from the free end. The resilient member is configured to take on a stretched configuration inside an endoscope during delivery. Alternatively or additionally, the devices include a cinch that is configured to snugly hold portions of both legs to force the legs closer together. | 09-17-2015 |
Shaz Qadeer, Seattle, WA US
Patent application number | Description | Published |
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20080271042 | TESTING MULTI-THREAD SOFTWARE USING PRIORITIZED CONTEXT SWITCH LIMITS - Testing multithreaded application programs for errors can be carried out in an efficient and productive manner at least in part by prioritizing thread schedules based on numbers of context switches between threads therein. In particular, each thread schedule in a multithreaded application program can be prioritized based on whether a given thread schedule has the same as or less than some maximum value. A model checker module can then iteratively execute thread schedules that fit within a given context switch maximum value, or a progressively higher value up to some limit. In one implementation, for example, the model checker module executes all thread schedules that have zero preempting context switches, then all thread schedules that have only one preempting context switch, etc. Most errors in an application program can be identified by executing only those thread schedule with relatively few preempting context switches. | 10-30-2008 |
20090178044 | FAIR STATELESS MODEL CHECKING - Techniques for providing a fair stateless model checker are disclosed. In some aspects, a schedule is generated to allocate resources for threads of a multi-thread program in lieu of having an operating system allocate resources for the threads. The generated schedule is both fair and exhaustive. In an embodiment, a priority graph may be implemented to reschedule a thread when a different thread is determined not to be making progress. A model checker may then implement one of the generated schedules in the program in order to determine if a bug or a livelock occurs during the particular execution of the program. An output by the model checker may facilitate identifying bugs and/or livelocks, or authenticate a program as operating correctly. | 07-09-2009 |
20100169868 | Unifying Type Checking and Property Checking for Low Level Programs - This document describes a unified type checker and property checker for a low level program's heap and its types. The type checker can use the full power of the property checker to express and verify subtle, program specific type and memory safety invariants well beyond what the native low level program system can check. Meanwhile, the property checker can rely on the type checker to provide structure and disambiguation for the program's heap, enabling more concise and more powerful type-based specifications. This approach makes use of a fully automated Satisfiability Modulo Theories (SMT) solver and a decision procedure for checking type safety, which means that the programmer's only duty is to provide high-level type and property annotations as part of the original program's source. | 07-01-2010 |
20140258986 | Identifying Implicit Assumptions Associated with a Software Product - A framework is described herein for identifying implicit assumptions associated with an SDK and its accompanying documentation (e.g., dev guide). An implicit assumption is information that is not expressly stated in the documentation, but which would be useful in assisting an application developer in building an application. The framework also describes a systematic approach for identifying one or more vulnerability patterns based on the identified implicit assumptions. An application developer may run a test on an application that is being developed to ensure that it does not have any deficiency which matches a vulnerability pattern. | 09-11-2014 |
Shaz Qadeer, Mercer Island, WA US
Patent application number | Description | Published |
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20130239120 | CONCURRENT ASSERTION - A concurrency assertions system disclosed herein provides for atomic evaluation of an assertion expression by locking an assertion lock upon initiating an assertion and thereby protecting the assertion evaluation from concurrent modifications to the variables in the assertion expressions. When a violation of an assertion is detected, the concurrency assertions system ensures that the exception statistics at the time of the assertion violation represents a program state where the assertion is violated, thus improving analysis of assertion violations. Furthermore, the concurrency assertions system continuously evaluates an expression for an assertion for a time period while other threads in the program are being executed. | 09-12-2013 |
20130241941 | STATIC VERIFICATION OF PARALLEL PROGRAM CODE - A symbolic encoding of predicated execution for static verification, based on a plurality of data parallel program instructions, is obtained. A result of static verification of one or more attributes associated with the plurality of data parallel program instructions is obtained, based on the symbolic encoding. | 09-19-2013 |
20140096112 | IDENTIFYING EXECUTION PATHS THAT SATISFY REACHABILITY QUERIES - Various technologies pertaining to answering reachability queries are described herein. A reachability query includes a user-specified destination line of code in source code that is desirably analyzed. A theorem prover is employed to identify an execution path through the source code that reaches the destination line of code. Graphical data is presented to the user that illustrates to the user the execution path through the source code that reaches the destination line of code. | 04-03-2014 |
Wajahat Qadeer, Menlo Park, CA US
Patent application number | Description | Published |
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20150086134 | LOW POWER PROGRAMMABLE IMAGE PROCESSOR - A convolution image processor includes a load and store unit, a shift register unit, and a mapping unit. The load and store unit is configured to load and store image pixel data and allow for unaligned access of the image pixel data. The shift register is configured to load and store at least a portion of the image pixel data from the load and store unit and concurrently provide access to each image pixel value in the portion of the image pixel data. The mapping unit is configured to generate a number of shifted versions of image pixel data and corresponding stencil data from the portion of the image pixel data, and concurrently perform one or more operations on each image pixel value in the shifted versions of the portion of the image pixel data and a corresponding stencil value in the corresponding stencil data. | 03-26-2015 |