Patent application number | Description | Published |
20090006755 | Providing application-level information for use in cache management - In one embodiment, the present invention includes a method for associating a first identifier with data stored by a first agent in a cache line of a cache to indicate the identity of the first agent, and storing the first identifier with the data in the cache line and updating at least one of a plurality of counters associated with the first agent in a metadata storage in the cache, where the counter includes information regarding inter-agent interaction with respect to the cache line. Other embodiments are described and claimed. | 01-01-2009 |
20100191993 | LOGICAL POWER THROTTLING - A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages. | 07-29-2010 |
20100299479 | OBSCURING MEMORY ACCESS PATTERNS - For each memory location in a set of memory locations associated with a thread, setting an indication associated with the memory location to request a signal if data from the memory location is evicted from a cache; and in response to the signal, reloading the set of memory locations into the cache. | 11-25-2010 |
20110087867 | PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION - A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed. | 04-14-2011 |
20110264866 | TECHNIQUE FOR USING MEMORY ATTRIBUTES - A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner. | 10-27-2011 |
20120084536 | PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION - A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed. | 04-05-2012 |
20120317588 | METHOD AND MESSAGE HANDLING HARDWARE STRUCTURE FOR VIRTUALIZATION AND ISOLATION OF PARTITIONS - A computer-based method configures a hardware circuit to transfer a message to a message queue in an operating system. The hardware circuit is used to transfer a message to the message queue in the operating system without requiring use of either the operating system or a hypervisor associated with the operating system. The using the hardware circuit uses a logical identifier associated with the message to select an entry in a mapping table of the hardware circuit. A value in the entry in the mapping table is used to select an entry in an action table. The entry in the action table is used to determine a tail pointer for the message queue. The hardware circuit appends the message to a location indicted by the tail pointer without requiring cycles of a hypervisor associated with the strand. | 12-13-2012 |
20120331314 | LOGICAL POWER THROTTLING - A processor includes a device providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core in the processor includes a pipeline having a decode pipe; and a logical power throttling unit coupled to the device to receive the output signal, and coupled to the decode pipe. Following the logical power throttling unit receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling unit causes the decode pipe to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages. | 12-27-2012 |
20130073835 | PRIMITIVES TO ENHANCE THREAD-LEVEL SPECULATION - A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed. | 03-21-2013 |
20140025901 | TECHNIQUE FOR USING MEMORY ATTRIBUTES - A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner. | 01-23-2014 |
20140150521 | System and Method for Calibrating Inertial Measurement Units - Inertial measurement units attached to a non-rigid body may measure a common motion event when the body changes direction of travel. Acceleration measurements made by the inertial measurement units of the event are used to determine a common reference direction which in turn can be used to derive, individually for each inertial measurement unit, a new orientation intended to be a better representation of the actual orientation of the inertial measurement unit. | 06-05-2014 |
20140163412 | MYOGRAPHY METHOD AND SYSTEM - A myography system and method can compensate for background noise in order to analyze data indicative of muscle contraction. Compensating for background noise may include any of: removing a model of the actual background noise from frequency data obtained from a myography sensor, identifying which myography sensor from among a plurality of myography sensors is located at a muscle likely undergoing contraction, and narrowing the analysis to searching for the type of muscular contraction (e.g., concentric, isometric, or eccentric) that is likely to be occurring. A model of the actual background noise can be obtained through use of myography sensors on different parts of the moving body. The muscles which are likely to be under contraction and the types of muscle contraction that are likely to be occurring at those muscles can be identified through use of motion capture devices, such as imaging devices and inertial measurement units. | 06-12-2014 |
20150040111 | HANDLING PRECOMPILED BINARIES IN A HARDWARE ACCELERATED SOFTWARE TRANSACTIONAL MEMORY SYSTEM - A method and apparatus for enabling a Software Transactional Memory (STM) with precompiled binaries is herein described. Upon encountering an access operation in a transaction, an annotation field associated with a memory location referenced by the access is checked. In response to the memory location representing a previous similar access within the transaction, the access is performed without access barriers. However, if the annotation field is in a default state representing no previous access during a pendancy of the transaction, then a mode of the processor is determined. If the processor mode is in implicit mode, an access handler/barrier is asynchronously executed. Conversely, in an explicit mode, a flag is set instead of asynchronously executing the handler. In addition, during compilation convert explicit and convert implicit instructions are inserted to intelligently convert modes for precompiled and newly compiled binaries. Furthermore, new versions of newly compiled functions may be inserted to provide strong atomicity between previously and newly compiled functions. | 02-05-2015 |