Patent application number | Description | Published |
20080238736 | BINARY-TO-BCD CONVERSION - Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value. | 10-02-2008 |
20090003589 | Native Composite-Field AES Encryption/Decryption Accelerator Circuit - A system comprises reception of input data of a Galois field GF(2 | 01-01-2009 |
20090168767 | MULTI-CORE PROCESSOR AND METHOD OF COMMUNICATING ACROSS A DIE - A multi-core die is provided that allows packets to be communicated across the die using resources of a packet switched network and a circuit switched network. | 07-02-2009 |
20090172068 | METHOD AND APPARATUS FOR EFFICIENTLY IMPLEMENTING THE ADVANCED ENCRYPTION STANDARD - Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((2 | 07-02-2009 |
20120328097 | APPARATUS AND METHOD FOR SKEIN HASHING - Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data. | 12-27-2012 |
20140013082 | RECONFIGURABLE DEVICE FOR REPOSITIONING DATA WITHIN A DATA WORD - Disclosed is a system and device and related methods for data manipulation, especially for SIMD operations such as permute, shift, and rotate. An apparatus includes a permute section that repositions data on sub-word boundaries and a shift section that repositions the data distances smaller than the sub-word width. The sub-word width is configurable and selectable, and the permute section and shift section may operate on different boundary widths. In a first stage, the permute section repositions the data at the nearest sub-word boundary and, in a second stage, the shift section repositions the data to its final desired position. The shift section includes multi-stages set in a logarithmic cascade relationship. Additionally, each shifter within each of the multi-stages is highly connected, allowing fast and precise data movements. | 01-09-2014 |
20140028677 | GRAPHICS LIGHTING ENGINE INCLUDING LOG AND ANTI-LOG UNITS - Disclosed is an apparatus and method for generating a lighting value based on a number of lighting factors. A lighting accelerator first converts an ambient portion, a diffuse light portion, and a specular light portion of the lighting factors into the log domain. Then, data combination units operate on the lighting factors after they have been converted. Then, the lighting factors are converted back from the log domain using anti-log processing. Converting the lighting factors into the log domain is accomplished by using a series of linear equations using coefficients that are all based on powers of two, and are therefore easily calculable. Further, while in the log domain, the specular light portion of the lighting factor is operated on by a special purpose multiplier that uses a truncated partial product tree, saving area and power with only a negligible amount of error. | 01-30-2014 |
20140201540 | SECURE KEY STORAGE USING PHYSICALLY UNCLONABLE FUNCTIONS - Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor. | 07-17-2014 |
20150086007 | COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT - Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area. | 03-26-2015 |