Patent application number | Description | Published |
20130024724 | PROCESSOR AND METHOD OF CONTROLLING EXECUTION OF PROCESSES - A processor includes a plurality of processing sections, each of which executes a predetermined process. A plurality of fault detecting circuits are respectively provided for the plurality of processing sections, to detect a fault in one of the plurality of processing sections as a fault processing section to generate a fault detection signal. A fault monitoring and control section controls a normal processing section as at least one of the plurality of processing sections other than the fault processing section to execute a relieving process in response to the fault detection signal. The relieving process is determined based on a process load of the fault processing section, a process load of the normal processing section, and priority levels of processes to be executed by the fault processing section and the normal processing section. | 01-24-2013 |
20130026613 | SEMICONDUCTOR DEVICE - A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region. | 01-31-2013 |
20130032930 | SEMICONDUCTOR DEVICE COMPRISING THROUGH-ELECTRODE INTERCONNECT - A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect. | 02-07-2013 |
20130038131 | SEMICONDUCTOR DEVICE TO SELECT A POWER SUPPLY - A power supply selection/detection circuit to select one main power supply from a plurality of external power supplies includes a resistance element with one end connected to an external power supply and another end connected to the main power supply, a first voltage detector to receive a voltage of the external power supply and detect a voltage of the external power supply, a second voltage detector to detect a voltage between the ends of the resistance element, and a switch connected between the external power supply and a ground to short-circuit or open-circuit between the external power supply and the ground according to an output of the second voltage detector. The resistance element and the first voltage detector are disposed for each of the plurality of external power supplies, and the second voltage detector and the switch are disposed for at least one of the plurality of external power supplies. | 02-14-2013 |
20130040434 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - In a semiconductor device having element isolation made of a trench-type isolating oxide film | 02-14-2013 |
20130062697 | SEMICONDUCTOR DEVICE - A semiconductor device capable of dissipating heat, which has been produced in an ESD protection element, to the exterior of the device rapidly and efficiently includes an ESD protection element having a drain region, a source region and a gate electrode, and a thermal diffusion portion. The thermal diffusion portion, which has been formed on the drain region, has a metal layer electrically connected to a pad, and contacts connecting the drain region and metal layer. The metal layer has a first wiring trace extending along the gate electrode, and second wiring traces intersecting the first wiring trace perpendicularly. The contacts are connected to intersections between the first wiring trace and the second wiring traces. Heat that has been produced at a pn-junction of the ESD protection element and transferred through a contact is diffused simultaneously in three directions through the first wiring trace and second wiring trace in the metal layer and is released into the pad. | 03-14-2013 |
20130073753 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic. | 03-21-2013 |
20130076911 | SOLID-STATE IMAGING APPARATUS, IMAGING METHOD, AND IMAGING SYSTEM - A solid-state imaging apparatus | 03-28-2013 |
20130093044 | SEMICONDUCTOR DEVICE - A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (≧2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m≧n≧2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal. | 04-18-2013 |
20130093096 | SEMICONDUCTOR DEVICE - A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern. | 04-18-2013 |
20130093508 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device comprises I/O cells arranged around a core region. Each of the I/O cells comprises a level shifter circuit, an I/O logic circuit, and an I/O buffer circuit. An I/O logic region in which the I/O logic circuit is arranged and an I/O buffer region in which the I/O buffer circuit is arranged overlap with a region in which a pad for the I/O cell is arranged. The I/O logic region and the I/O buffer region are arranged side by side in a direction parallel to a side of the core region. | 04-18-2013 |
20130099390 | ELECTRONIC DEVICE - In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer. | 04-25-2013 |
20130113525 | SEMICONDUCTOR DEVICE AND OPERATION MODE SWITCH METHOD - A semiconductor device includes a first internal terminal, a first transistor, a second transistor, an oscillator including an output terminal to output a clock signal, and a comparator coupled to a first internal terminal, and that compares a potential of the first internal terminal when the first internal terminal is coupled to the first reference potential with a potential of the first internal terminal when the first internal terminal is coupled to a second reference potential, an external terminal being connectable to the first internal terminal, and a second internal terminal being coupled to the external terminal, and that receives an input signal through the external terminal. Each of the first control terminal and the second control terminal is coupled to the output terminal to commonly receive the clock signal. The first transistor and the second transistor exclusively operate according to the clock signal. | 05-09-2013 |
20130115737 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH OUTER LEADS HAVING A LEAD-FREE PLATING - A semiconductor device has a tab having a semiconductor chip fixed thereto, a plurality of inner leads, a plurality of outer leads formed integrally with the inner leads, a plurality of wires coupling the electrode pads of the semiconductor chip to the inner leads, and a molded body having the semiconductor chip molded therein. Over a surface of each of the outer leads protruding from the molded body, an outer plating including lead-free platings is formed. The outer plating has, in a thickness direction thereof, a first lead-free plating and a second lead-free plating, the first and second lead-free platings having the same composition and meeting at an interface. The first and second lead-free platings are formed under different conditions and may have different physical properties. | 05-09-2013 |
20130127033 | SEMICONDUCTOR DEVICE - A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area. | 05-23-2013 |
20130127068 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first interconnection including a first end, a second interconnection connected to the first interconnection and including a width being gradually wider towards the first end, a third interconnection and a fourth interconnection, the third interconnection and the fourth interconnection being arranged to sandwich the second interconnection. The first interconnection, the second interconnection, the third interconnection, and the fourth interconnection are each formed in a same layer and a width of the first interconnection is wider than a width of the second interconnection. | 05-23-2013 |
20130130442 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area. | 05-23-2013 |
20130132448 | MEMORY SYSTEM FOR PORTABLE TELEPHONE - A memory system is constituted of a file storage flash memory storing a control program required for a control portion and a large amount of data, and a random access memory storing a program used by the control portion and functioning as a buffer memory for received data. Thus, a memory system for a portable telephone capable of storing a large amount of received data at high-speed and allowing reading of the stored data at high-speed is provided. | 05-23-2013 |
20130132916 | BEHAVIORAL SYNTHESIS METHOD, BEHAVIORAL SYNTHESIS PROGRAM AND BEHAVIORAL SYNTHESIS APPARATUS - A behavioral synthesis method according to the present invention includes generating a scheduled CDFG based on behavioral description information, generating a lifetime for each variable based on the scheduled CDFG, selecting m variables whose lifetimes do not overlap on a time axis, allocating a first register to a first variable having a first bit width and bits of the first bit width within another variable, allocating a second register to bits other than the bits of the first bit width within another variable, and outputting circuit information of a synthesized circuit including the first and second registers. | 05-23-2013 |
20130134510 | SEMICONDUCTOR DEVICE - In the interior of a semiconductor substrate having a main surface, a first p | 05-30-2013 |
20130140709 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a technique adopting a TSV technique, capable of improving manufacturing yield and reliability of semiconductor devices. By partitioning a connection pad-forming region into a plurality of regions and by forming, respectively, connection pads | 06-06-2013 |
20130140714 | SEMICONDUCTOR DEVICE - In a QFN that includes a die pad, a semiconductor chip mounted on the die pad, a plurality of leads arranged around the semiconductor chip, a plurality of wires that electrically connect the plurality of electrode pads of the semiconductor chip with the plurality of leads, respectively, and a sealing member sealing the semiconductor chip and the plurality of wires, first and second step portions are formed at shifted positions on the left and right sides of each of the leads to make the positions of the first and second step portions shifted between the adjacent leads. As a result, the gap between the leads is narrowed, thereby achieving the miniaturization or the increase in the number of pins of the QFN. | 06-06-2013 |
20130141999 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits. | 06-06-2013 |
20130147010 | SEMICONDUCTOR DEVICE - A semiconductor device ( | 06-13-2013 |
20130149854 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other. | 06-13-2013 |
20130151226 | CIRCUIT SIMULATION METHOD - By considering a Deep Nwell diffusing into a Pwell region, accuracy of a substrate parasitic-resistance extraction is improved. A well region of a semiconductor integrated circuit where a Pwell and a Deep Nwell are formed in a substrate is divided into two or more meshes each including two or more resistor segments and a substrate noise is analyzed based thereon. In this regard, parallel components of resistors coupling the Pwell with the substrate are deleted in accordance with a state of the Deep Nwell diffusing into the Pwell region, so that an arithmetic processing unit executes a process for expressing a rise in the resistance value. By deleting the parallel components of the resistors coupling the Pwell with the substrate, the rise in the resistance value caused by the Deep Nwell can be reflected in the substrate parasitic-resistance extraction. Therefore, the accuracy of the substrate parasitic-resistance extraction can be improved. | 06-13-2013 |
20130153887 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - An interlayer insulating film is formed. Then a first gate electrode and a second gate electrode are buried in the interlayer insulating film. Then, an anti-diffusion film is formed over the interlayer insulating film, over the first gate electrode, and over the second gate electrode. Then, a first semiconductor layer is formed over the anti-diffusion film which is present over the first gate electrode. Then, an insulating cover film is formed over the upper surface and on the lateral side of the first semiconductor layer and over the anti-diffusion film. Then, a semiconductor film is formed over the insulating cover film. Then, the semiconductor film is removed selectively to leave a portion positioned over the second gate electrode, thereby forming a second semiconductor layer. | 06-20-2013 |
20130153888 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device provided with an active element in a multilayer interconnect layer and decreased in a chip area. A second interconnect layer is provided over a first interconnect layer. A first interlayer insulating layer is provided in the first interconnect layer. A semiconductor layer is provided in a second interconnect layer and in contact with the first interlayer insulating layer. A gate insulating film is provided over the semiconductor layer. A gate electrode is provided over the gate insulating film. At least two first vias are provided in the first interconnect layer and in contact by way of upper ends thereof with the semiconductor layer. | 06-20-2013 |
20130154706 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area. | 06-20-2013 |
20130154735 | RF POWER AMPLIFIER AND OPERATING METHOD THEREOF - The present invention reduces the size of a power detection circuit. An RF power amplifier includes an RF amplifier circuit and a power detection circuit. The RF amplifier circuit subjects an RF input signal having a predetermined frequency band to power amplification and generates an RF amplifier output signal. The input terminal of the power detection circuit is coupled to the output of the RF amplifier circuit. The power detection circuit detects a harmonic component having a harmonic frequency that is a whole number multiple of the frequency of a fundamental wave component of the RF amplifier output signal, and generates at an output terminal a detected signal indicative of the signal level of the fundamental wave component of the RF amplifier output signal. The power detection circuit includes an input circuit, which detects the harmonic component, and an output circuit, which generates the detected signal at the output. | 06-20-2013 |
20130163599 | ALIGNMENT CIRCUIT AND RECEIVING APPARATUS - A control circuit generates a selection signal indicating a head area of an alignment buffer when the area is an unwritten area, and when the head area is a written area, successively performs comparison between a sequence number stored in the area and a sequence number of a target packet from a head to a tail to search a boundary area and generates a selection signal indicating the detected boundary area. When the boundary area could not be detected even when the search reaches the last written area, the control circuit generates a selection signal indicating the next area of the last written area. The writing circuit shifts data stored in each area by one area from the area indicated by the selection signal in a direction of the tail of the alignment buffer, and writes packet information of the target packet into the area indicated by the selection signal. | 06-27-2013 |
20130163609 | SERIAL COMMUNICATION DEVICE AND SERIAL COMMUNICATION METHOD - A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal. | 06-27-2013 |
20130169247 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance. | 07-04-2013 |
20130175574 | IE TYPE TRENCH GATE IGBT - In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween. | 07-11-2013 |
20130178061 | METHOD OF MANUFACTURING POROUS FILM AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - First, a porous insulating film | 07-11-2013 |
20130179966 | PASSWORD AUTHENTICATION CIRCUIT AND METHOD - A password authentication circuit includes a timer that measures first and second periods of a password authentication period, a control circuit that, in a first period, disables writing of a password received into a password register, in a predetermined period within a second period enables writing of a password received into the password register and outside the predetermined period within the second period disables writing of a password received into the password register; a password comparison unit that compares a password in the password register and a password expected value to perform authentication of the password; and a first period generation unit that controls variably the first period, a password last written into the password register in the predetermined period of the second period being made a target for authentication. | 07-11-2013 |
20130181221 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A circuit including an inverter is provided for a wiring layer. | 07-18-2013 |
20130181324 | SEMICONDUCTOR DEVICE - A semiconductor device sends and receives electrical signals. The semiconductor device includes a first substrate provided with a first circuit region containing a first circuit; a multi-level interconnect structure provided on the first substrate; a first inductor provided in the multi-level interconnect structure so as to include the first circuit region; and a second inductor provided in the multi-level interconnect structure so as to include the first circuit region, wherein one of the first inductor and the second inductor is connected to the first circuit and the other of the first inductor and the second inductor is connected to a second circuit. | 07-18-2013 |
20130182839 | SEMICONDUCTOR DEVICE AND IC CARD - In power residue calculation in a primality determination, in addition to the conventional randomization of an exponent, a modulus is also randomized. A random number generated by a random number generator is set to a randomizing number, and is input to a modulus generator and an exponent generator. The modulus generator and the exponent generator randomize a prime number candidate P using the randomizing number to generate a randomized modulus R | 07-18-2013 |
20130185083 | AUDIO ENCODING APPARATUS - There is provided an audio encoding apparatus that can avoid that audio data becomes irreproducible after fast-forward play. A quantization unit quantizes and buffers audio data into a buffer unit. A stream generating unit puts buffered audio data in a frame where there is a header related to the audio data in a stream and/or in one or plural frames preceding that frame. As for a predetermined frame, the stream generating unit puts in a data field of the frame the whole of an audio data piece related to a header included in that frame and puts audio sample data following that audio sample in a remaining part of the data field. As for a frame not a predetermined one, it puts in a data field of the frame an audio data piece related to a header included in that frame and/or audio data pieces following that audio data piece. | 07-18-2013 |
20130189819 | METHOD OF MANUFACTURING VERTICAL PLANAR POWER MOSFET AND METHOD OF MANUFACTURING TRENCH-GATE POWER MOSFET - In the manufacturing steps of a super-junction power MOSFET having a drift region having a super junction structure, after the super junction structure is formed, introduction of a body region and the like and heat treatment related thereto are typically performed. However, in the process thereof, a dopant in each of P-type column regions and the like included in the super junction structure is diffused to result in a scattered dopant profile. This causes problems such as degradation of a breakdown voltage when a reverse bias voltage is applied between a drain and a source and an increase in ON resistance. According to the present invention, in a method of manufacturing a silicon-based vertical planar power MOSFET, a body region forming a channel region is formed by selective epitaxial growth. | 07-25-2013 |
20130193899 | MOTOR DRIVE CONTROL DEVICE AND OPERATING METHOD THEREOF - The present invention properly starts up various types of motors under operating conditions where motor operations are performed in a wide range of temperature and power supply voltage. Output drive controllers supply PWM drive output signals to the output pre-driver in such a manner as to minimize the error between a current instruction signal and a current detection digital signal. In response to a detected induced voltage generated from a voltage detector upon startup of a motor, an initial acceleration controller supplies initial acceleration output signals specifying a conducting phase for initial acceleration of the motor to the output drive controllers. The initial acceleration controller, the output drive controllers, and an output driver make a conducting phase change and perform a PWM drive to provide the initial acceleration of the motor in response to the detected induced voltage and to an error upon startup of the motor. Upper-limit duty values for the PWM drive output signals to be supplied from the output drive controllers to the output pre-driver during the period of the initial acceleration can be arbitrarily set in the output drive controllers. | 08-01-2013 |
20130195147 | RADIO COMMUNICATION APPARATUS - An apparatus includes: an offset adjustment unit supplying an offset correction signal corresponding to a frequency switching to an adder unit receiving output from a mixer; a timing adjustment unit adjusting the timing of a frequency switching signal supplied to a local oscillator and the timing of an offset correction amount switching signal supplied to the offset adjustment unit for changing an offset amount in correspondence with the frequency switching in the local oscillator; a noise amount measurement and calculation unit receiving a signal obtained by amplifying and filtering the signal from the adder unit, to measure a noise amount of the signal and generates a timing determination signal based on the noise amount; and a control unit controlling frequency switching signal timing and the offset correction amount switching signal supplied to the timing adjustment unit, based on the timing determination signal from the noise amount measurement and calculation unit. | 08-01-2013 |
20130196607 | LEVEL SHIFT CIRCUIT - A level shift circuit includes a first pair of transistors of the first conductive type (M | 08-01-2013 |
20130200363 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - There is provided a readily manufacturable semiconductor device including two transistors having mutually different characteristics. The semiconductor device includes a substrate, a multilayer wiring layer disposed over the substrate, a first transistor disposed in the multilayer wiring layer, and a second transistor disposed in a layer different from a layer including the first transistor disposed therein of the multilayer wiring layer, and having different characteristics from those of the first transistor. This can provide a readily manufacturable semiconductor device including two transistors having mutually different characteristics. | 08-08-2013 |
20130200472 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The performances of semiconductor elements disposed in a multilayer wiring layer are improved. A semiconductor device includes: a first wire disposed in a first wiring layer; a second wire disposed in a second wiring layer stacked over the first wiring layer; a gate electrode arranged between the first wire and the second wire in the direction of stacking of the first wiring layer and the second wiring layer, and not coupled with the first wire and the second wire; a gate insulation film disposed over the side surface of the gate electrode; and a semiconductor layer disposed over the side surface of the gate electrode via the gate insulation film, and coupled with the first wire and the second wire. | 08-08-2013 |
20130203361 | SEMICONDUCTOR DEVICE AND COMMUNICATION SYSTEM INCLUDING THE SAME - Disclosed is a semiconductor device including a semiconductor chip and a semiconductor package. The semiconductor package includes an antenna formed of a lead frame, a first wire that connects the antenna and a first electrode pad of the semiconductor chip, and a second wire that connects the antenna and a second electrode pad of the semiconductor chip. The semiconductor chip is disposed in one of four regions in the semiconductor package sectioned by line segments connecting midpoints of two pairs of opposing sides of the semiconductor package. A centroid of the semiconductor chip is positioned outside a closed curve composed of a straight line segment connecting a first connection point where the antenna and the first wire are connected and a second connection point where the antenna and the second wire are connected, and a line connecting the first and second connection points along the antenna. | 08-08-2013 |