Patent application number | Description | Published |
20090017584 | PROCESS FOR FINFET SPACER FORMATION - A process for finFET spacer formation generally includes depositing, in order, a conformnal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure; tilt implanting dopant ions into portions of the capping layer about the gate structure; selectively removing undoped capping material about the source and drain regions; selectively removing exposed portions of the spacer material; selectively removing exposed portions of the capping material; anisotropically removing a portion of the spacer material so as to expose a top surface of the gate material and isolate the spacer material to sidewalls of the gate structure; and removing the oxide liner from the fin to form the spacer on the finFET structure. | 01-15-2009 |
20090047791 | SEMICONDUCTOR ETCHING METHODS - A method of etching semiconductor structures is disclosed. The method may include etching an SRAM portion of a semiconductor device, the method comprising: providing a silicon substrate layer, a nitride layer thereover, an optical dispersive layer over the nitride layer, and a silicon anti-reflective coating layer thereover; etching the silicon anti-reflective coating layer using an image layer; removing the image layer; etching the optical dispersive layer while removing the silicon anti-reflective coating layer; etching the optical dispersive layer and the nitride layer simultaneously; and etching the optical dispersive layer, the nitride layer, and the silicon substrate simultaneously. | 02-19-2009 |
20090098737 | METHOD OF PATTERNING MULTILAYER METAL GATE STRUCTURES FOR CMOS DEVICES - A method of forming patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices includes performing a first etch process to remove exposed portions of a polysilicon layer included within a gate stack, the polysilicon layer formed on a metal layer also included within the gate stack; oxidizing an exposed top portion of the metal layer following the first etch process so as to create an metal oxide layer having an etch selectivity with respect to the polysilicon layer; removing the metal oxide layer through a combination of a physical ion bombardment thereof, and the introduction of an isotropic chemical component thereto so as to prevent oxide material at bottom corners of the polysilicon layer; and performing a second etch process to remove exposed portions of the metal layer. | 04-16-2009 |
20090104776 | METHODS FOR FORMING NESTED AND ISOLATED LINES IN SEMICONDUCTOR DEVICES - A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein the photoresist defines a line, etching the layer of antireflective coating and the layer of polysilicon using RIE with a low bias power, removing the photoresist, removing the layer of antireflective coating, etching the STI film stack to form the line, wherein the layer of polysilicon further defines the line. | 04-23-2009 |
20100029082 | METHOD AND APPARATUS FOR ANGULAR HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION - Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well. | 02-04-2010 |
20100258881 | DUAL METAL AND DUAL DIELECTRIC INTEGRATION FOR METAL HIGH-K FETS - The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region. | 10-14-2010 |
20110180880 | DUAL METAL AND DUAL DIELECTRIC INTEGRATION FOR METAL HIGH-K FETS - The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region. | 07-28-2011 |
20120139061 | Self-Aligned Contact For Replacement Gate Devices - A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure. | 06-07-2012 |
20120288687 | EDGE PROTECTION SEAL FOR BONDED SUBSTRATES - A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring. | 11-15-2012 |
20120306093 | CONVERTING METAL MASK TO METAL-OXIDE ETCH STOP LAYER AND RELATED SEMICONDUCTOR STRUCTURE - A method includes providing a semiconductor structure including a plurality of devices; depositing a nitride cap over the semiconductor structure; forming an aluminum mask over the nitride cap, the aluminum mask including a plurality of first openings; converting the aluminum mask to an aluminum oxide etch stop layer; and performing middle-of-line fabrication processing, leaving the aluminum oxide etch stop layer in place. A semiconductor structure includes a plurality of devices on a substrate; a nitride cap over the plurality of devices; an aluminum oxide etch stop layer over the nitride cap; an inter-level dielectric (ILD) over the aluminum oxide etch stop layer; and a plurality of contacts extending through the ILD, the aluminum oxide etch stop layer and the nitride cap to the plurality of devices. | 12-06-2012 |
20130168017 | EDGE PROTECTION SEAL FOR BONDED SUBSTRATES - A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring. | 07-04-2013 |
20130175587 | SELF-ALIGNED CONTACT FOR REPLACEMENT GATE DEVICES - A conductive top surface of a replacement gate stack is recessed relative to a top surface of a planarization dielectric layer by at least one etch. A dielectric capping layer is deposited over the planarization dielectric layer and the top surface of the replacement gate stack so that the top surface of a portion of the dielectric capping layer over the replacement gate stack is vertically recessed relative to another portion of the dielectric layer above the planarization dielectric layer. The vertical offset of the dielectric capping layer can be employed in conjunction with selective via etch processes to form a self-aligned contact structure. | 07-11-2013 |
20130277764 | Etch Stop Layer Formation In Metal Gate Process - A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor. | 10-24-2013 |
20130277767 | ETCH STOP LAYER FORMATION IN METAL GATE PROCESS - A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor. | 10-24-2013 |
20140103404 | REPLACEMENT GATE WITH AN INNER DIELECTRIC SPACER - After formation of source and drain regions and a planarization dielectric layer, a disposable gate structure is removed to form a gate cavity. A gate dielectric and a lower gate electrode are formed within the gate cavity. The lower gate electrode is vertically recessed relative to the planarization dielectric layer to form a recessed region. An inner dielectric spacer is formed within the recessed region by depositing a conformal dielectric layer and removing horizontal portions thereof by an anisotropic etch. An upper gate electrode is formed by depositing another conductive material within a remaining portion of the recessed region. A contact level dielectric layer is formed and contact structures are formed to the source and drain regions. The inner dielectric spacer prevents an electrical short between the gate electrode and a contact structure that partially overlies the gate electrode by overlay variations during lithographic processes. | 04-17-2014 |
20140193755 | Amplification Method For Photoresist Exposure In Semiconductor Chip Manufacturing - An electrical field is applied through an extreme ultraviolet (EUV) photoresist layer along a direction perpendicular to an interface between the EUV photoresist layer and an underlying layer. Secondary electrons and thermal electrons are accelerated along the direction of the electrical field, and travel with directionality before interacting with the photoresist material for a chemical reaction. The directionality increases the efficiency of electron photoacid capture, reducing the required EUV dose for exposure. Furthermore, this directionality reduces lateral diffusion of the secondary and thermal electrons, and thereby reduces blurring of the image and improves the image resolution of feature edges formed in the EUV photoresist layer. The electrical field may be generated by applying a direct current (DC) and/or alternating current (AC) bias voltage across an electrostatic chuck and a conductive plate placed over the EUV photoresist layer with a hole for passing the EUV radiation through. | 07-10-2014 |
20140262039 | METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS - A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer. | 09-18-2014 |
20140291761 | Asymmetric Spacers - A semiconductor device having asymmetric spacers and steps for forming the same are disclosed. The spacers have difference capacitances, with the spacer having a higher capacitance formed over a source region of the device and the spacer having a lower capacitance formed over a drain region of the device. Embodiments of the disclosed invention include spacers made from different materials, having different or substantially equal thicknesses. | 10-02-2014 |
20140295674 | ANGLED GAS CLUSTER ION BEAM - An angled gas cluster ion beam (“GCIB”) and methods for using the same are disclosed. Gas clusters are ionized to create a gas cluster beam directed towards a semiconductor wafer. The semiconductor wafer is positioned so that it intercepts the gas cluster beam at an angle that is non-perpendicular to the beam, so that the gas cluster ions in the beam react with structures on the semiconductor wafer asymmetrically, allowing for asymmetrical deposition on or etching of material thereon. According to one embodiment, GCIB is used to form asymmetric spacers having different materials, different thicknesses, or both. | 10-02-2014 |
20150042972 | AMPLIFICATION METHOD FOR PHOTORESIST EXPOSURE IN SEMICONDUCTOR CHIP MANUFACTURING - An electrical field is applied through an extreme ultraviolet (EUV) photoresist layer along a direction perpendicular to an interface between the EUV photoresist layer and an underlying layer. Secondary electrons and thermal electrons are accelerated along the direction of the electrical field, and travel with directionality before interacting with the photoresist material for a chemical reaction. The directionality increases the efficiency of electron photoacid capture, reducing the required EUV dose for exposure. Furthermore, this directionality reduces lateral diffusion of the secondary and thermal electrons, and thereby reduces blurring of the image and improves the image resolution of feature edges formed in the EUV photoresist layer. The electrical field may be generated by applying a direct current (DC) and/or alternating current (AC) bias voltage across an electrostatic chuck and a conductive plate placed over the EUV photoresist layer with a hole for passing the EUV radiation through. | 02-12-2015 |
Patent application number | Description | Published |
20120256299 | ARC RESIDUE-FREE ETCHING - Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer. | 10-11-2012 |
20130200441 | INTEGRATED CIRCUIT CONTACT STRUCTURE AND METHOD - An integrated circuit having a mis-alignment tolerant electrical contact is formed by providing a semiconductor containing substrate over which is a first FET gate laterally bounded by a first dielectric region, replacing an upper portion of the first FET gate with a second dielectric region, applying a mask having an opening extending partly over an adjacent source or drain contact region of the substrate and over a part of the second dielectric region above the first FET gate, forming an opening through the first dielectric region extending to the contact region and the part of the second dielectric region, and filling the opening with a conductor making electrical connection with the contact region but electrically insulated from the first FET gate by the second dielectric region. A further FET gate may also be provided having an electrical contact thereto formed separately from the source-drain contact. | 08-08-2013 |
20130200471 | ALIGNMENT TOLERANT SEMICONDUCTOR CONTACT AND METHOD - An alignment tolerant electrical contact is formed by providing a substrate on which is a first electrically conductive region (e.g., a MOSFET gate) having an upper surface, the first electrically conductive region being laterally bounded by a first dielectric region, applying a mask having an opening extending partly over a contact region (e.g., for the MOSFET source or drain) on the substrate and over a part of the upper surface, forming a passage through the first dielectric region extending to the contact region and the part of the upper surface, thereby exposing the contact region and the part of the upper surface, converting the part of the upper surface to a second dielectric region and filling the opening with a conductor making electrical contact with the contact region but electrically insulated from the electrically conductive region by the second dielectric region. | 08-08-2013 |
20150054179 | ARC RESIDUE-FREE ETCHING - Antireflective residues during pattern transfer and consequential short circuiting are eliminated by employing an underlying sacrificial layer to ensure complete removal of the antireflective layer. Embodiments include forming a hard mask layer over a conductive layer, e.g., a silicon substrate, forming the sacrificial layer over the hard mask layer, forming an optical dispersive layer over the sacrificial layer, forming a silicon anti-reflective coating layer over the optical dispersive layer, forming a photoresist layer over the silicon anti-reflective coating layer, where the photoresist layer defines a pattern, etching to transfer the pattern to the hard mask layer, and stripping at least the optical dispersive layer and the sacrificial layer. | 02-26-2015 |