Patent application number | Description | Published |
20080219380 | Data Encoding in a Clocked Data Interface - One embodiment of the present invention includes a data transmission system. The system comprises a data transmitter that provides a plurality of data bits over at least one data line. The data transmitter comprises a clock that provides a clock signal associated with timing for latching the plurality of data bits and a data encoder configured to encode error data associated with the data transmission system in the clock signal. | 09-11-2008 |
20090021283 | HIGH SPEED LATCHED COMPARATOR - An improved latched comparator, including a track mode circuit, a latch and a latch and track select circuit. The track mode circuit includes two transistors having their sources connected together, and their respective gates receiving a respective first and second input, and their drains connected to the power supply by respective resistors. The latch includes a further two transistors having their sources connected together, a gate of each connected to a drain of the other, and their drains connected to a respective one of the common connection node of the first transistor and the first resistor, and the second transistor and the second resistor. The latch and track select circuit includes a further transistor having an source connected to a current sink connected to ground, having a gate connected to receive a track signal and having a drain connected to the common connection node of the first and second transistors, and a still further transistor having a source connected to the current sink connected to ground, having a gate connected to receive a latch signal and having a drain connected to the common connection node of the third and fourth transistors. Bipolar embodiments are also included. | 01-22-2009 |
20090219059 | TRACK-AND-HOLD CIRCUIT WITH LOW DISTORTION - A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit. The RC network receives the analog input signal and is scaled to change the location of a zero to reduce the signal-dependence of the sampling instant. | 09-03-2009 |
20090219060 | METHOD AND APPARATUS OF SFDR ENHANCEMENT - A track-and-hold or sample-and-hold (S/H) circuit for an analog-to-digital converter (ADC) is provided. A difference between the disclosed S/H circuit and conventional S/H circuits is the use of a peaking circuit. This peaking circuit generally provides increased current to switching transistor when transitioning between track and hold which can increase the Spurious-Free Dynamic Range (SFDR) as low frequencies, by as much as 15 dB. | 09-03-2009 |
20100213986 | CLOCK BUFFER - An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage. Additionally, the first and second clamps is coupled to the collectors of the first, second, third, and fourth BJTs. | 08-26-2010 |
20100214144 | ERROR CORRECTION METHOD AND APPARATUS - A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output impedance. Included with the switched current source is an error correction transistor and a resistor that cooperate to feed a current back through a bias transistor to correct an error that generally results from the current gains or β's of transistors within the switched current source. To accomplish this, however, the resistor is selected to have a value that is sufficiently large such that current from the error correction transistor flows back through the bias transistor. | 08-26-2010 |
20110018750 | ERROR CORRECTION METHOD AND APPARATUS - A switched current source is provided. The switched current source is generally comprised of transistors and resistors, and the source has a high output impedance. Included with the switched current source is an error correction transistor and a resistor that cooperate to feed a current back through a bias transistor to correct an error that generally results from the current gains or β's of transistors within the switched current source. To accomplish this, however, the resistor is selected to have a value that is sufficiently large such that current from the error correction transistor flows back through the bias transistor. | 01-27-2011 |
20110043257 | TRACK-AND-HOLD CIRCUIT WITH LOW DISTORTION - A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit. The RC network receives the analog input signal and is scaled to change the location of a zero to reduce the signal-dependence of the sampling instant. | 02-24-2011 |
20110121868 | CLOCK BUFFER - An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage. Additionally, the first and second clamps is coupled to the collectors of the first, second, third, and fourth BJTs. | 05-26-2011 |
20120044004 | TRACK AND HOLD ARCHITECTURE WITH TUNABLE BANDWIDTH - To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths. | 02-23-2012 |
20120062402 | MULTIPLEXED AMPLIFIER WITH REDUCED GLITCHING - In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths. | 03-15-2012 |
20120092199 | PIPELINED ADC HAVING A THREE-LEVEL DAC ELEMENTS - In conventional pipelined analog-to-digital converters (ADCs), it is common to employ digital-to-analog converters (DACs) in the ADC stages that use two-state switches or segments. A problem with this arrangement is that for each DAC state there is a noise contribution from each DAC switch, resulting from its current source. Here, however, a DAC is employed that uses three-state DAC switches, which reduces the noise contributions from the DAC switches' current sources and reduces the amount of area used. | 04-19-2012 |
20120280720 | INTRA-PAIR SKEW CANCELLATION TECHNIQUE FOR DIFFERENTIAL SIGNALING - A method for deskewing a differential signal is provided. A common-mode voltage of a differential signal and an average for the common-mode voltage of the differential signal are measured. A difference between first and second portions of the differential signal is determined, and deskew information is derived from the common-mode voltage and the average. The deskew information can then be combined with the difference to deskew the differential signal. | 11-08-2012 |
20130015990 | TRACK AND HOLD ARCHITECTURE WITH TUNABLE BANDWIDTH - To date, bandwidth mismatch within time-interleaved (TI) analog-to-digital converters (ADCs) has been largely ignored because compensation for bandwidth mismatch is performed by digital post-processing, namely finite impulse response filters. However, the lag from digital post-processing is prohibitive in high speed systems, indicating a need for blind mismatch compensation. Even with blind bandwidth mismatch estimation, though, adjustment of the filter characteristics of track-and-hold (T/H) circuits within the TI ADCs can be difficult. Here, a T/H circuit architecture is provided that uses variations of the gate voltage of a sampling switch (which varies the “on” resistance of the sampling switch) to change the bandwidth of the T/H circuits so as to precisely match the bandwidths. | 01-17-2013 |
20130021188 | MULTIPLEXED AMPLIFIER WITH REDUCED GLITCHING - In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths. | 01-24-2013 |
20130038480 | TRACK-AND-HOLD CIRCUIT WITH LOW DISTORTION - A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit. The RC network receives the analog input signal and is scaled to change the location of a zero to reduce the signal-dependence of the sampling instant. | 02-14-2013 |
20130099824 | REDUCED OFFSET COMPARATOR - An apparatus is provided. The apparatus comprises backend circuitry and pairs of redundant input circuits. Each pair of redundant input circuits is configured to form a differential pair of transistors, and each redundant input circuit includes a multiplexer and a set of transistors. The multiplexer is coupled to the backend circuitry, and each transistor from the set of transistors has a first passive electrode, a second passive electrode, and a control electrode. The first passive electrode of each transistor from the set of transistors is coupled to the multiplexer, and the control electrodes from the set of transistors are coupled together. | 04-25-2013 |
20130101000 | METHOD AND APPARATUS FOR PERFORMING SPECULATIVE DECISION FEEDBACK EQUALIZATION - A method for equalizing a received signal is provided. The signal is filtered and transmitted over a channel using an encoding scheme, where the encoding scheme has transmit symbols. This transmitted signal is then shaped such that the filtering and equalization adjust a set of taps in an equalization window so that the taps from the set are substantially equal to one another. Inter-symbol interference is then compensated for in the equalized signal using a speculative DFE with significantly reduced comparator levels. | 04-25-2013 |
20130147520 | COMPARATOR WITH IMPROVED TIME CONSTANT - An apparatus for comparing differential input signal inputs is provided. The apparatus comprises a CMOS sense amplifier (which has having a first input terminal, a second input terminal, a first output terminal, and a second output terminal), a first output circuit (which has a first load capacitance), a second output circuit (which has a second load capacitance), and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier. | 06-13-2013 |
20130148702 | METHOD AND APPARATUS FOR INPUT SIGNAL OFFSET COMPENSATION - A method for compensator for comparator offset is provided. A first propagation delay for a first signal traversing a comparator to a first output terminal of the comparator and a second propagation delay for a second signal traversing the comparator to a second output terminal of the comparator are measured. The first and second propagation delays are then compared to generate a comparison result, and the comparator is adjusted to compensate for an input voltage offset based at least in part on the comparison result. | 06-13-2013 |
20130265732 | INTERCHIP COMMUNICATION USING A DIELECTRIC WAVEGUIDE - An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide. | 10-10-2013 |
20130265733 | INTERCHIP COMMUNICATION USING AN EMBEDDED DIELECTRIC WAVEGUIDE - An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide. | 10-10-2013 |
20130265734 | INTERCHIP COMMUNICATION USING EMBEDDED DIELECTRIC AND METAL WAVEGUIDES - An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide. | 10-10-2013 |
20140072024 | CARRIER RECOVERY IN AMPLITUDE AND PHASE MODULATED SYSTEMS - A method is provided. A multi-amplitude signal is received and downconverted so as to generate I and Q signals using a local oscillator signal. The I and Q signals are equalized, and the equalized I and Q signals are digitized. First and second gains are adjusted with the second and first digital signals, respectively, and applied to the equalized I and Q signals, respectively. The difference between the first and second amplified signals is determined, and an error signal is generated from the difference between the first and second amplified signals. The local oscillator signal is then adjusted with the error signal. | 03-13-2014 |