Patent application number | Description | Published |
20140191296 | SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES - Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed. | 07-10-2014 |
20140353734 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATION WITH REDUCED GATE AND CONTACT RESISTANCES - Semiconductor structures with reduced gate and/or contact resistances and fabrication methods are provided. The method includes: providing a semiconductor device, which includes forming a transistor of the semiconductor device, where the transistor forming includes: forming a T-shaped gate for the transistor, the T-shaped gate being T-shaped in elevational cross-section; and forming an inverted-T-shaped contact to an active region of the transistor, the inverted-T-shaped contact including a conductive structure with an inverted T-shape in elevational cross-section. | 12-04-2014 |
20150061040 | SELF-ALIGNED DIELECTRIC ISOLATION FOR FINFET DEVICES - Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed. | 03-05-2015 |
20150102410 | SEMICONDUCTOR DEVICE INCLUDING STRESS LAYER ADJACENT CHANNEL AND RELATED METHODS - A method for making a semiconductor device may include forming a gate on a semiconductor layer, forming sidewall spacers adjacent the gate, and forming raised source and drain regions defining a channel in the semiconductor layer under the gate. The raised source and drain regions may be spaced apart from the gate by the sidewall spacers. The method may further include removing the sidewall spacers to expose the semiconductor layer between the raised source and drain regions and the gate, and forming a stress layer overlying the gate and the raised source and drain regions. The stress layer may contact the semiconductor layer between the raised source and drain regions and the gate. | 04-16-2015 |
20150108573 | SEMICONDUCTOR DEVICE INCLUDING VERTICALLY SPACED SEMICONDUCTOR CHANNEL STRUCTURES AND RELATED METHODS - A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures. | 04-23-2015 |
20150115370 | SEMICONDUCTOR DEVICE PROVIDING ENHANCED FIN ISOLATION AND RELATED METHODS - A method for making a semiconductor device may include forming a first semiconductor layer on a substrate comprising a first semiconductor material, forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material, and forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate. The method may further include forming an oxide layer laterally surrounding the pillars and mask regions, and removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar. The method may additionally include etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar, and removing the inner spacers and forming an oxide beneath each semiconductor fin. | 04-30-2015 |
20150187896 | SILICIDE PROTECTION DURING CONTACT METALLIZATION AND RESULTING SEMICONDUCTOR STRUCTURES - A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact. | 07-02-2015 |
20150187945 | SALICIDE PROTECTION DURING CONTACT METALLIZATION AND RESULTING SEMICONDUCTOR STRUCTURES - A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A gate is provided above the channel region. A silicon nitride protective layer is provided over the source region and the drain region, along with a silicon nitride cap over the gate region. The silicon nitride protective layer is configured to allow punch-through of the protective layer after source and drain openings are created, while preventing etching through the cap above the gate. The self-aligned source, drain and gate contacts are formed while protecting the source and drain salicide using the silicon nitride protective layer and gate cap. | 07-02-2015 |