Patent application number | Description | Published |
20110223774 | REDUCED PATTERN LOADING USING BIS(DIETHYLAMINO)SILANE (C8H22N2Si) AS SILICON PRECURSOR - Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications. | 09-15-2011 |
20120058281 | METHODS FOR FORMING LOW MOISTURE DIELECTRIC FILMS - A method for forming a pre-metal dielectric (PMD) layer or an inter-metal dielectric (IMD) layer over a substrate includes placing the substrate in a chemical vapor deposition (CVD) process chamber and forming a first oxide layer over the substrate in the CVD process chamber. The first oxide layer is formed using a thermal CVD process at a temperature of about 450° C. or less and a sub-atmospheric pressure. The method also includes forming a second oxide layer over the first oxide layer in the CVD process chamber. The second oxide layer is formed using a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of about 450° C. or less and a sub-atmospheric pressure. The substrate remains in the CVD process chamber during formation of the first oxide layer and the second oxide layer. | 03-08-2012 |
20120085733 | SELF ALIGNED TRIPLE PATTERNING - Embodiments of the present invention pertain to methods of forming features on a substrate using a self-aligned triple patterning (SATP) process. A stack of layers is patterned near the optical resolution of a photolithography system using a high-resolution photomask. The heterogeneous stacks are selectively etched to undercut a hard mask layer beneath overlying cores. A dielectric layer, which is flowable during formation, is deposited and fills the undercut regions as well as the regions between the heterogeneous stacks. The dielectric layer is anisotropically etched and a conformal spacer is deposited on and between the cores. The spacer is anisotropically etched to leave two spacers between each core. The cores are stripped and the spacers are used together with the remaining hard mask features to pattern the substrate at triple the density of the original pattern. | 04-12-2012 |
20130048605 | DOUBLE PATTERNING ETCHING PROCESS - A method of etching a substrate comprises forming on the substrate, a plurality of double patterning features composed of silicon oxide, silicon nitride, or silicon oxynitride. The substrate having the double patterning features is provided to a process zone. An etching gas comprising nitrogen tri-fluoride, ammonia and hydrogen is energized in a remote chamber. The energized etching gas is introduced into the process zone to etch the double patterning features to form a solid residue on the substrate. The solid residue is sublimated by heating the substrate to a temperature of at least about 100° C. | 02-28-2013 |
20130102149 | LINER PROPERTY IMPROVEMENT - Methods of forming a dielectric liner layer on a semiconductor substrate are described. The method may include flowing a phosphorus-containing precursor with a silicon-containing precursor and an oxygen-containing precursor over the substrate to deposit a dielectric material. The dielectric material may be deposited along a field region and within at least one via on the substrate having a depth of at least 1 μm. The method may also include forming a liner layer within the via with the dielectric material. The liner may include a silicon oxide doped with phosphorus, and the thickness of the liner layer at an upper portion of the via sidewall may be less than about 5 times the thickness of the liner layer at a lower portion of the via sidewall. | 04-25-2013 |
20130260533 | INTRENCH PROFILE - A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1. | 10-03-2013 |
20130260564 | INSENSITIVE DRY REMOVAL PROCESS FOR SEMICONDUCTOR INTEGRATION - Methods of depositing and etching dielectric layers from a surface of a semiconductor substrate are disclosed. The methods may include depositing a first dielectric layer having a first wet etch rate in aqueous HF. The methods also may include depositing a second dielectric layer that may be initially flowable following deposition, and the second dielectric layer may have a second wet etch rate in aqueous HF that is higher than the first wet etch rate. The methods may further include etching the first and second dielectric layers with an etchant gas mixture, where the first and second dielectric layers have a ratio of etch rates that is closer to one than the ratio of the second wet etch rate to the first wet etch rate in aqueous HF. | 10-03-2013 |
20140273451 | TUNGSTEN DEPOSITION SEQUENCE - Methods of filling gaps with tungsten are described. The methods include a tungsten dep-etch-dep sequence to enhance gapfilling yet avoid difficulty in restarting deposition after the intervening etch. The first tungsten deposition may have a nucleation layer or seeding layer to assist growth of the first tungsten deposition. Restarting deposition with a less-than-conductive nucleation layer would impact function of an integrated circuit, and therefore avoiding tungsten “poisoning” during the etch is desirable. The etching step may be performed using a plasma to excite a halogen-containing precursor while the substrate at relatively low temperature (near room temperature or less). The plasma may be local or remote. Another method may be used in combination or separately and involves the introduction of a source of oxygen into the plasma in combination with the halogen-containing precursor. | 09-18-2014 |
20150031211 | INTRENCH PROFILE - A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1. | 01-29-2015 |
Patent application number | Description | Published |
20080311753 | OXYGEN SACVD TO FORM SACRIFICAL OXIDE LINERS IN SUBSTRATE GAPS - A method of forming and removing a sacrificial oxide layer is described. The method includes forming a step on a substrate, where the step has a top and sidewalls. The method may also include forming the sacrificial oxide layer around the step by chemical vapor deposition of molecular oxygen and TEOS, where the oxide layer is formed on the top and sidewalls of the step. The method may also include removing a top portion of the oxide layer and the step; removing a portion of the substrate exposed by the removal of the step to form a etched substrate; and removing the entire sacrificial oxide layer from the etched substrate. | 12-18-2008 |
20090031953 | CHEMICAL VAPOR DEPOSITION OF HIGH QUALITY FLOW-LIKE SILICON DIOXIDE USING A SILICON CONTAINING PRECURSOR AND ATOMIC OXYGEN - Methods of depositing a silicon oxide layer on a substrate are described. The methods may include the steps of providing a substrate to a deposition chamber, generating an atomic oxygen precursor outside the deposition chamber, and introducing the atomic oxygen precursor into the chamber. The methods may also include introducing a silicon precursor to the deposition chamber, where the silicon precursor and the atomic oxygen precursor are first mixed in the chamber. The silicon precursor and the atomic oxygen precursor react to form the silicon oxide layer on the substrate, and the deposited silicon oxide layer may be annealed. Systems to deposit a silicon oxide layer on a substrate are also described. | 02-05-2009 |
20110053380 | SILICON-SELECTIVE DRY ETCH FOR CARBON-CONTAINING FILMS - A method of etching silicon-and-carbon-containing material is described and includes a SiConi™ etch in combination with a flow of reactive oxygen. The reactive oxygen may be introduced before the SiConi™ etch reducing the carbon content in the near surface region and allowing the SiConi™ etch to proceed more rapidly. Alternatively, reactive oxygen may be introduced during the SiConi™ etch further improving the effective etch rate. | 03-03-2011 |
20110223760 | CONFORMALITY OF OXIDE LAYERS ALONG SIDEWALLS OF DEEP VIAS - A method for improving conformality of oxide layers along sidewalls of vias in semiconductor substrates includes forming a nitride layer over an upper surface of a semiconductor substrate and forming a via extending through the nitride layer and into the semiconductor substrate. The via may have a depth of at least about 50 μm from a top surface of the nitride layer and an opening of less than about 10 μm at the top surface of the nitride layer. The method also includes forming an oxide layer over the nitride layer and along sidewalls and bottom of the via. The oxide layer may be formed using a thermal chemical vapor deposition (CVD) process at a temperature of less than about 450° C., where a thickness of the oxide layer at the bottom of the via is at least about 50% of a thickness of the oxide layer at the top surface of the nitride layer. | 09-15-2011 |
Patent application number | Description | Published |
20140152238 | SMART CART - An interactive surgical device storage and supply cart is provided and includes a top storage assembly having multiple storage containers for various size product packages, a bottom storage assembly having drawers to retain larger packages of sterilized devices and an intermediate shelf having storage trays for frequently used items. One or more batter chargers are provided on the cart to supply fully charged batteries. A docking station is provided on the cart to receive computers for inventory management and display instructional material. The docking station also can receive communication devices for consultation with outside sources in real time. Additionally, a power strip is provided to power the battery charger (s) and docking station as well as other auxiliary, powered devices and instruments. | 06-05-2014 |
20150076206 | APPARATUS AND METHOD FOR DIFFERENTIATING BETWEEN TISSUE AND MECHANICAL OBSTRUCTION IN A SURGICAL INSTRUMENT - A surgical instrument is provided. The surgical instrument includes: a handle assembly; a jaw assembly comprising a staple cartridge containing a plurality of staples and an anvil to form the plurality of staples upon firing; a drive assembly at least partially located within the handle and connected to the jaw assembly and the lockout mechanism; a motor disposed within the handle assembly and operatively coupled to the drive assembly; and a controller operatively coupled to the motor, the controller configured to control supply of electrical current to the motor and to monitor a current draw of the motor, wherein the controller is further configured to terminate the supply of electrical current to the motor in response to a rate of change of the current draw indicative of a mechanical limit of at least one of the jaw assembly, the drive assembly, or the motor. | 03-19-2015 |
20150080912 | APPARATUS AND METHOD FOR DIFFERENTIATING BETWEEN TISSUE AND MECHANICAL OBSTRUCTION IN A SURGICAL INSTRUMENT - A surgical instrument is provided. The surgical instrument includes: a handle assembly; a jaw assembly comprising a staple cartridge containing a plurality of staples and an anvil to form the plurality of staples upon firing; a drive assembly at least partially located within the handle and connected to the jaw assembly and the lockout mechanism; a motor disposed within the handle assembly and operatively coupled to the drive assembly; and a controller operatively coupled to the motor, the controller configured to control supply of electrical current to the motor and to monitor a current draw of the motor, wherein the controller is further configured to terminate the supply of electrical current to the motor in response to a rate of change of the current draw indicative of a mechanical limit of at least one of the jaw assembly, the drive assembly, or the motor. | 03-19-2015 |