Satya
Akella V.s. Satya, Milpitas, CA US
Patent application number | Description | Published |
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20080237487 | MULTIPLE DIRECTIONAL SCANS OF TEST STRUCTURES ON SEMICONDUCTOR INTEGRATED CIRCUITS - Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect. | 10-02-2008 |
20080246030 | TEST STRUCTURES AND METHODS FOR INSPECTION OF SEMICONDUCTOR INTEGRATED CIRCUITS - Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area. | 10-09-2008 |
Murali Mohan Baggu Datta Venkata Satya, Glenville, NY US
Patent application number | Description | Published |
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20150112496 | METHODS AND SYSTEMS FOR CONTROLLING AN ELECTRIC NETWORK - A method and system for use in controlling an electric network are provided. The system includes an Integrated Volt-VAr Control (IVVC) component configured to determine optimization parameters for slow dynamics electromechanical devices and fast dynamics DER devices coupled to the network. The slow dynamics devices are controlled by a present state of the electric network and a voltage rise table that is adaptively updated in real-time using a command output, or a power flow-based complete optimization routine that generates optimal setpoints for the traditional controllable assets and for at least some of the fast dynamics DER devices. The fast dynamics devices are controlled locally using a control algorithm that uses a reactive power contribution based on IVVC settings, based on photo-voltaic (PV) plant active power variations, based on power factor, or based on a voltage of the local electric network. | 04-23-2015 |
Padma A. Satya, Milpitas, CA US
Patent application number | Description | Published |
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20080237487 | MULTIPLE DIRECTIONAL SCANS OF TEST STRUCTURES ON SEMICONDUCTOR INTEGRATED CIRCUITS - Disclosed is a method of inspecting a sample. The sample is scanned in a first direction with at least one particle beam. The sample is scanned in a second direction with at least one particle beam. The second direction is at an angle to the first direction. The number of defects per an area of the sample are found as a result of the first scan, and the position of one or more of the found defects is determined from the second scan. In a specific embodiment, the sample includes a test structure having a plurality of test elements thereon. A first portion of the test elements is exposed to the beam during the first scan to identify test elements having defects, and a second portion of the test elements is exposed during the second scan to isolate and characterize the defect. | 10-02-2008 |
20080246030 | TEST STRUCTURES AND METHODS FOR INSPECTION OF SEMICONDUCTOR INTEGRATED CIRCUITS - Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area. | 10-09-2008 |
Ravi Vijaya Satya, Montgomery Village, MD US
Patent application number | Description | Published |
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20150225775 | PCR PRIMERS - The present disclosure provides methods, compositions, and kits for performing PCR (including multiplex PCR). The methods, compositions and kits provided herein use one or more primer pairs that contain one or more cleavable bases located at a minimal distance away from the 3′ termini of the primers, and increase the accuracy of downstream analysis of sequence data. | 08-13-2015 |
Sharma Satya, Setauket, NY US
Patent application number | Description | Published |
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20110163871 | RFID MONITORING OF DRUG REGIMEN COMPLIANCE - Disclosed is an apparatus and system for monitoring drug regimen compliance, the system utilizing a Radio Frequency Identification (RfID) tag affixed to a pharmaceutical agent and a wearable RFID reader that identifies a patient. The RFID tag identifies the pharmaceutical agent and the RFID reader wirelessly communicates with a central monitoring system upon ingestion of the pharmaceutical agent. | 07-07-2011 |
Srinivas Satya, Sunnyvale, CA US
Patent application number | Description | Published |
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20130192524 | Continuous Substrate Processing System - A processing chamber having a plurality of movable substrate carriers stacked therein for continuously processing a plurality of substrates is provided. The movable substrate carrier is capable of being transported from outside of the processing chamber, e.g., being transferred from a load luck chamber, into the processing chamber and out of the processing chamber, e.g., being transferred into another load luck chamber. Process gases delivered into the processing chamber are spatially separated into a plurality of processing slots, and/or temporally controlled. The processing chamber can be part of a multi-chamber substrate processing system. | 08-01-2013 |
20130192761 | Rotary Substrate Processing System - A substrate processing system for processing multiple substrates is provided and generally includes at least one processing platform and at least one staging platform. Each substrate is positioned on a substrate carrier disposed on a substrate support assembly. Multiple substrate carriers, each is configured to carry a substrate thereon, are positioned on the surface of the substrate support assembly. The processing platform and the staging platform, each includes a separate substrate support assembly, which can be rotated by a separate rotary track mechanism. Each rotary track mechanism is capable of supporting the substrate support assembly and continuously rotating multiple substrates carried by the substrate carriers and disposed on the substrate support assembly. Each substrate is thus processed through at least one shower head station and at least one buffer station, which are positioned at a distance above the rotary track mechanism of the processing platform. Each substrate can be transferred between the processing platform and the staging platform and in and out the substrate processing system. | 08-01-2013 |
20130196078 | Multi-Chamber Substrate Processing System - A substrate processing system for processing multiple substrates is provided and generally includes at least one substrate processing platform and at least one substrate staging platform. The substrate processing platform includes a rotary track system capable of supporting multiple substrate support assemblies and continuously rotating the substrate support assemblies, each carrying a substrate thereon. Each substrate is positioned on a substrates support assembly disposed on the rotary track system and being processed through at least one shower head station and at least one buffer station, which are positioned atop the rotary track system of the substrate processing platform. Multiple substrates disposed on the substrate support assemblies are processed in and out the substrate processing platform. The substrate staging platform includes at least one dual-substrate processing station, each dual-substrate processing station includes two substrate support assemblies for supporting two substrates thereon. | 08-01-2013 |
Srinivas Ayyalasomayajula Satya, Maharashtra IN
Patent application number | Description | Published |
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20110257396 | PROCESS FOR THE MANUFACTURE OF CIS(-)-LAMIVUDINE - An improved process for the manufacture of Lamivudine. The process involves: | 10-20-2011 |