Patent application number | Description | Published |
20090077515 | Method of Constrained Aggressor Set Selection for Crosstalk Induced Noise - A preliminary static timing analysis run is performed to calculate the delay and slew as well as timing windows for each net in the design, followed by coupling analysis for each given aggressor-victim combination, and to calculate the noise effect on the timing of victim net. Given a set of functional groups that relate the coupled aggressors to each other, the worst set of aggressors are calculated that satisfy the constraints from the functional groups, based on the calculated impact of each aggressor on the victim. Similarly the set of aggressors which contribute to the maximum amount of inductive coupling noise effect on timing are calculated. Furthermore, the coupling noise impact of the reduced set of aggressors on the given victim line and adjust the delay value calculated in the preliminary static timing analysis run. | 03-19-2009 |
20090210839 | TIMING CLOSURE USING MULTIPLE TIMING RUNS WHICH DISTRIBUTE THE FREQUENCY OF IDENTIFIED FAILS PER TIMING CORNER - A method of timing closure for integrated circuit designs uses multiple timing runs which distribute the frequency of identified fails per timing corner (between starting timing corners and remaining timing corners) to maximize efficiency in timing analysis. More specifically, the method closes timing for a chosen set of starting timing corners, verifies the remaining timing corners are orthogonal to the starting timing corners, closes timing for the remaining timing corners using multi-corner analysis, and verifies that all timing corners have positive slack margin. | 08-20-2009 |
20090243630 | METHOD TO QUICKLY ESTIMATE INDUCTANCE FOR TIMING MODELS - A method of estimating an inductance delay includes determining a resistance-capacitance (RC) delay with resistances and capacitances of a network and estimating an inductance delay of the network by determining a propagation delay of an electromagnetic (EM) field across wires of the network. Additionally, the method includes determining if the RC delay is below a specified threshold and adding the estimated inductance delay to the RC delay to determine a total time to propagate voltage swings through the network if the RC delay is below the specified threshold. | 10-01-2009 |
20090307645 | METHOD AND SYSTEM FOR ANALYZING CROSS-TALK COUPLING NOISE EVENTS IN BLOCK-BASED STATISTICAL STATIC TIMING - A method of performing statistical timing analysis of a logic design, including effects of signal coupling, includes performing a deterministic analysis to determine deterministic coupling information for at least one aggressor/victim net pair of the logic design. Additionally, the method includes performing a statistical timing analysis in which the deterministic coupling information for the at least one aggressor/victim net pair is combined with statistical values of the statistical timing analysis to determine a statistical effective capacitance of a victim of the aggressor/victim net pair. Furthermore, the method includes using the statistical effective capacitance to determine timing data used in the statistical timing analysis. | 12-10-2009 |
Patent application number | Description | Published |
20090004792 | METHOD FOR FORMING A DUAL METAL GATE STRUCTURE - A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer. | 01-01-2009 |
20090029538 | PROCESS FOR MAKING A SEMICONDUCTOR DEVICE USING PARTIAL ETCHING - A method including partially etching a first portion of a first layer, wherein the first layer is a conductive layer, is provided. The method further includes removing at least a portion of a second layer. The method further includes completing etching of said first portion of the conductive layer so that said first portion of the conductive layer is removed. The method further includes completing formation of the semiconductor device. | 01-29-2009 |
20110073964 | SEMICONDUCTOR DEVICE WITH OXYGEN-DIFFUSION BARRIER LAYER AND METHOD FOR FABRICATING SAME - Methods and apparatus are provided for fabricating a transistor. The transistor comprises a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and an oxygen-gettering conductive layer overlying the high-k dielectric layer. The oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive layer. | 03-31-2011 |
20120104515 | TRANSISTORS AND SEMICONDUCTOR DEVICES WITH OXYGEN-DIFFUSION BARRIER LAYERS - Embodiments of transistors comprise a gate stack overlying a semiconductor material. The gate stack comprises a deposited oxide layer overlying the semiconductor material, an oxygen-diffusion barrier layer overlying the deposited oxide layer, a high-k dielectric layer overlying the oxygen-diffusion barrier layer, and a conductive material (e.g., an oxygen-gettering conductive material) overlying the high-k dielectric layer. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material. | 05-03-2012 |
Patent application number | Description | Published |
20110005378 | METHODS AND APPARATUS FOR PROVIDING BALLISTIC PROTECTION - Methods and apparatus for providing ballistic protection and stopping high-velocity rounds or explosives and for constructing protective structures. The apparatus includes a building block, one or more ballistic panels configured to fit within the building block, each ballistic panel includes a three-dimensional core that acts as a truss for the ballistic panel, and a filler. The filler fills in spaces defined by each three-dimensional core and any empty spaces in the building block. The one or more ballistic panels and the filler are inserted into the building block. The building block is shaped to interlock with other building blocks. | 01-13-2011 |
20110023693 | Methods and apparatus for providing ballistic protection - Methods and apparatus for providing ballistic protection and stopping high-velocity rounds or explosives and a secure trash can. These and other advantages may be provided by a secure trash can for containing explosions resulting from explosive devices deposited in the secure trash can. The secure trash can includes a curved wall, including an inner liner, a curved ballistic panel, including a three-dimensional core that defines spaces and acts as a truss for ballistic panel and a filler, the filler fills in spaces defined by the three-dimensional core, an outer layer, surrounding the curved ballistic panel, and a base, connected to the curved wall. The secure trash can may also include a lid, placed on the curved wall. | 02-03-2011 |